definitions.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

// ticks for setting non-overlapping clock period

`define PHI1_HIGH    #100
`define NON_OVLP_1_2  #25
`define PHI2_HIGH    #100
`define NON_OVLP_2_1  #25

// special reset address

`define FUNKY_ADDR 5'b11111

// commands

`define WRITE   2'b00
`define SEARCH  2'b01
`define READ    2'b10
`define DELETE  2'b11

// values for select line into address mux

`define ADDR_SEL_PRI 1'b0
`define ADDR_SEL_CAM 1'b1

// values for select line into data mux

`define DATA_SEL_RAM     1'b0
`define DATA_SEL_NOMATCH 1'b1

// subfields of data bus

`define CAM_DATA_MSB 15
`define CAM_DATA    15:0
`define CAM_DATA_15 14:0
`define CAM_MASK    19:16
`define RAM_DATA    22:20

// values for select lines into pads

`define PAD_SEL_IN  1'b0
`define PAD_SEL_OUT 1'b1

// CAM definitions

//`define CAM_SEARCH_ADDR 21
//`define CAM_RESET_ADDR 22
//`define CAM_ERROR_ADDR 26
`define CAM_SIZE 20

// Latch delay
`define LATCH_DELAY #0