datapath.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

`include "definitions.v"

module datapath(phi1_b, phi2_b, data_in_s1, lsb_addr_q1, msb_addr_s1,
                cam_wen_q1, valid_in_s1, cam_reset_s1, found_match_v2,
                addr_sel_s2, ram_wen_q2, data_sel_s1, no_match_s1, data_out_s1,
                valid_out_s1);

input phi1_b;
input phi2_b;
input [22:0] data_in_s1;
input [3:0] lsb_addr_q1;
input [4:0] msb_addr_s1;
input cam_wen_q1;
input valid_in_s1;
input cam_reset_s1;

output found_match_v2;
input addr_sel_s2;
input ram_wen_q2;

input data_sel_s1;
input [2:0] no_match_s1;
output [22:0] data_out_s1;
output valid_out_s1;

wire phi1 = ~phi1_b;
wire phi2 = ~phi2_b;

// each instance below is preceded by the wire
// declarations that it requires


wire [14:0] cam_true_bits_s1; // minus MSB, that goes direct from pad to CAM
wire [14:0] cam_false_bits_s1;
      
mask_decode mask_decode(
  data_in_s1[`CAM_MASK],
  data_in_s1[`CAM_DATA_15],
  cam_true_bits_s1, // decoder doesn't need to see MSB of data
  cam_false_bits_s1
);


wire [19:0] cam_dec_addr_q1;
wire [16:0] cam_data_out_s1;
wire [14:0] cam_mask_out_s1;
wire [19:0] cam_match_s1;

cam cam(
  cam_wen_q1,
  lsb_addr_q1,
  msb_addr_s1,
  cam_dec_addr_q1,
  {valid_in_s1, data_in_s1[`CAM_DATA_MSB], cam_true_bits_s1},
  cam_false_bits_s1,
  cam_data_out_s1,
  cam_mask_out_s1,
  cam_match_s1,
  cam_reset_s1,
  phi1,
  phi2
);


wire [3:0] cam_mask_enc_s1;

mask_encode mask_encode(
  cam_mask_out_s1,
  cam_data_out_s1[14:0],
  cam_mask_enc_s1
);


wire [16:0] cam_data_out_s2;
wire [3:0] cam_mask_out_s2;

latch_21bit cam_latch_1(
  {cam_data_out_s1, cam_mask_enc_s1},
  {cam_data_out_s2, cam_mask_out_s2},
  phi1
);


latch_21bit cam_latch_2(
  {cam_data_out_s2, cam_mask_out_s2},
  {valid_out_s1, data_out_s1[`CAM_DATA], data_out_s1[`CAM_MASK]},
  phi2
);


wire [19:0] dec_addr_s2;

latch_20bit addr_latch(
  cam_dec_addr_q1,
  dec_addr_s2,
  phi1
);


wire [19:0] cam_match_s2;

latch_20bit match_latch(
  cam_match_s1,
  cam_match_s2,
  phi1
);


wire [19:0] pri_addr_v2;

priority priority(
  cam_match_s2,
  pri_addr_v2,
  found_match_v2,
  phi1,
  phi2
);


wire [19:0] amx_addr_v2;

addr_mux addr_mux(
  addr_sel_s2,
  pri_addr_v2,
  dec_addr_s2,
  amx_addr_v2
);


wire [2:0] ram_data_s1;

ram ram(
  ram_wen_q2,
  amx_addr_v2,
  data_in_s1[`RAM_DATA],
  ram_data_s1,
  phi1,
  phi2
);

data_mux data_mux(
  data_sel_s1,
  ram_data_s1,
  no_match_s1,
  data_out_s1[`RAM_DATA]
);

endmodule // datapath