snoop.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

// Produced by /usr/class/ee272/bin/snoopgen from file snoop.in

// Remember to run Verilog with -x if any variables are subscripted


// 2 Clock phases: phi1 phi2
// Input, Verilog: no_match_s1, irsim: no_match_s1, vector[2:0]
// Input, Verilog: data_sel_s1, irsim: data_sel_s1
// Input, Verilog: ram_wen_q2, irsim: ram_wen_q2
// Input, Verilog: addr_sel_s2, irsim: addr_sel_s2
// Input, Verilog: cam_reset_s1, irsim: cam_reset_s1
// Input, Verilog: valid_in_s1, irsim: valid_in_s1
// Input, Verilog: cam_wen_q1, irsim: cam_wen_q1
// Input, Verilog: msb_addr_s1, irsim: msb_addr_s1, vector[4:0]
// Input, Verilog: lsb_addr_q1, irsim: lsb_addr_q1, vector[3:0]
// Input, Verilog: data_in_s1, irsim: data_in_s1, vector[22:0]
// Input, Verilog: phi2, irsim: core_phi2
// Input, Verilog: phi1, irsim: core_phi1
// Output, Verilog: valid_out_s1, irsim: valid_out_s1, Stable phase 1
// Output, Verilog: data_out_s1, irsim: data_out_s1, vector[22:0], Stable phase 1
// Output, Verilog: found_match_v2, irsim: found_match_v2, Valid phase 2


module snooper(
	phi1, phi2, data_in_s1, lsb_addr_q1, 
	msb_addr_s1, cam_wen_q1, valid_in_s1, cam_reset_s1, 
	found_match_v2, addr_sel_s2, ram_wen_q2, data_sel_s1, 
	no_match_s1, data_out_s1, valid_out_s1);

input phi1;
input phi2;
input [22:0] data_in_s1;
input [3:0] lsb_addr_q1;
input [4:0] msb_addr_s1;
input cam_wen_q1;
input valid_in_s1;
input cam_reset_s1;
input found_match_v2;
input addr_sel_s2;
input ram_wen_q2;
input data_sel_s1;
input [2:0] no_match_s1;
input [22:0] data_out_s1;
input valid_out_s1;

initial
begin
	$rsim_init();
	$rsim_check_on();
end

// One always block per input

always @(no_match_s1)
begin
	$rsim_log_input(no_match_s1[2], "no_match_s1[2]");
	$rsim_log_input(no_match_s1[1], "no_match_s1[1]");
	$rsim_log_input(no_match_s1[0], "no_match_s1[0]");
end
always @(data_sel_s1) $rsim_log_input(data_sel_s1, "data_sel_s1");
always @(ram_wen_q2) $rsim_log_input(ram_wen_q2, "ram_wen_q2");
always @(addr_sel_s2) $rsim_log_input(addr_sel_s2, "addr_sel_s2");
always @(cam_reset_s1) $rsim_log_input(cam_reset_s1, "cam_reset_s1");
always @(valid_in_s1) $rsim_log_input(valid_in_s1, "valid_in_s1");
always @(cam_wen_q1) $rsim_log_input(cam_wen_q1, "cam_wen_q1");
always @(msb_addr_s1)
begin
	$rsim_log_input(msb_addr_s1[4], "msb_addr_s1[4]");
	$rsim_log_input(msb_addr_s1[3], "msb_addr_s1[3]");
	$rsim_log_input(msb_addr_s1[2], "msb_addr_s1[2]");
	$rsim_log_input(msb_addr_s1[1], "msb_addr_s1[1]");
	$rsim_log_input(msb_addr_s1[0], "msb_addr_s1[0]");
end
always @(lsb_addr_q1)
begin
	$rsim_log_input(lsb_addr_q1[3], "lsb_addr_q1[3]");
	$rsim_log_input(lsb_addr_q1[2], "lsb_addr_q1[2]");
	$rsim_log_input(lsb_addr_q1[1], "lsb_addr_q1[1]");
	$rsim_log_input(lsb_addr_q1[0], "lsb_addr_q1[0]");
end
always @(data_in_s1)
begin
	$rsim_log_input(data_in_s1[22], "data_in_s1[22]");
	$rsim_log_input(data_in_s1[21], "data_in_s1[21]");
	$rsim_log_input(data_in_s1[20], "data_in_s1[20]");
	$rsim_log_input(data_in_s1[19], "data_in_s1[19]");
	$rsim_log_input(data_in_s1[18], "data_in_s1[18]");
	$rsim_log_input(data_in_s1[17], "data_in_s1[17]");
	$rsim_log_input(data_in_s1[16], "data_in_s1[16]");
	$rsim_log_input(data_in_s1[15], "data_in_s1[15]");
	$rsim_log_input(data_in_s1[14], "data_in_s1[14]");
	$rsim_log_input(data_in_s1[13], "data_in_s1[13]");
	$rsim_log_input(data_in_s1[12], "data_in_s1[12]");
	$rsim_log_input(data_in_s1[11], "data_in_s1[11]");
	$rsim_log_input(data_in_s1[10], "data_in_s1[10]");
	$rsim_log_input(data_in_s1[9], "data_in_s1[9]");
	$rsim_log_input(data_in_s1[8], "data_in_s1[8]");
	$rsim_log_input(data_in_s1[7], "data_in_s1[7]");
	$rsim_log_input(data_in_s1[6], "data_in_s1[6]");
	$rsim_log_input(data_in_s1[5], "data_in_s1[5]");
	$rsim_log_input(data_in_s1[4], "data_in_s1[4]");
	$rsim_log_input(data_in_s1[3], "data_in_s1[3]");
	$rsim_log_input(data_in_s1[2], "data_in_s1[2]");
	$rsim_log_input(data_in_s1[1], "data_in_s1[1]");
	$rsim_log_input(data_in_s1[0], "data_in_s1[0]");
end
always @(phi2) $rsim_log_input(phi2, "core_phi2");
always @(phi1) $rsim_log_input(phi1, "core_phi1");

// One always block per inout


// Let go of inouts


// Check stable signals

always @(phi1)
begin
	$rsim_log_output(valid_out_s1, "valid_out_s1");
	$rsim_log_output(data_out_s1[22], "data_out_s1[22]");
	$rsim_log_output(data_out_s1[21], "data_out_s1[21]");
	$rsim_log_output(data_out_s1[20], "data_out_s1[20]");
	$rsim_log_output(data_out_s1[19], "data_out_s1[19]");
	$rsim_log_output(data_out_s1[18], "data_out_s1[18]");
	$rsim_log_output(data_out_s1[17], "data_out_s1[17]");
	$rsim_log_output(data_out_s1[16], "data_out_s1[16]");
	$rsim_log_output(data_out_s1[15], "data_out_s1[15]");
	$rsim_log_output(data_out_s1[14], "data_out_s1[14]");
	$rsim_log_output(data_out_s1[13], "data_out_s1[13]");
	$rsim_log_output(data_out_s1[12], "data_out_s1[12]");
	$rsim_log_output(data_out_s1[11], "data_out_s1[11]");
	$rsim_log_output(data_out_s1[10], "data_out_s1[10]");
	$rsim_log_output(data_out_s1[9], "data_out_s1[9]");
	$rsim_log_output(data_out_s1[8], "data_out_s1[8]");
	$rsim_log_output(data_out_s1[7], "data_out_s1[7]");
	$rsim_log_output(data_out_s1[6], "data_out_s1[6]");
	$rsim_log_output(data_out_s1[5], "data_out_s1[5]");
	$rsim_log_output(data_out_s1[4], "data_out_s1[4]");
	$rsim_log_output(data_out_s1[3], "data_out_s1[3]");
	$rsim_log_output(data_out_s1[2], "data_out_s1[2]");
	$rsim_log_output(data_out_s1[1], "data_out_s1[1]");
	$rsim_log_output(data_out_s1[0], "data_out_s1[0]");
end

always @(phi2)
begin
end


// Check valid signals

always @(negedge phi1)
begin
end

always @(negedge phi2)
begin
	$rsim_log_output(found_match_v2, "found_match_v2");
end


// Check qualified signals

always @(phi1)
begin
end

always @(phi2)
begin
end



endmodule