mask_encode.v

来自「一个验证过的CAM源码（CAM=Content Address Memory）。」· Verilog 代码 · 共 42 行

module mask_encode(false_s1, true_s1, enc_s1);
input [14:0] false_s1;
input [14:0] true_s1;
output [3:0] enc_s1;

reg [14:0] tmp_dec_s1;
reg [3:0] enc_s1;
always @ (false_s1 or true_s1 or tmp_dec_s1)
begin
  // if both are 0s, mask is 1
  tmp_dec_s1 = ~true_s1 & ~false_s1;

  case (tmp_dec_s1)
    15'h0000: enc_s1 = 0;
    15'h0001: enc_s1 = 1;
    15'h0003: enc_s1 = 2;
    15'h0007: enc_s1 = 3;
    15'h000f: enc_s1 = 4;
    15'h001f: enc_s1 = 5;
    15'h003f: enc_s1 = 6;
    15'h007f: enc_s1 = 7;
    15'h00ff: enc_s1 = 8;
    15'h01ff: enc_s1 = 9;
    15'h03ff: enc_s1 = 10;
    15'h07ff: enc_s1 = 11;
    15'h0fff: enc_s1 = 12;
    15'h1fff: enc_s1 = 13;
    15'h3fff: enc_s1 = 14;
    15'h7fff: enc_s1 = 15;
    
    // this should never happen
    default: begin
      enc_s1 = 15;
      //$display("ERROR mask_encode at %d, tmp_dec_s1 = %x", $time, tmp_dec_s1);
    end
  endcase
end

endmodule // mask_encode