latch_21bit.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

`include "definitions.v"

module latch_21bit ( data_in, data_out, phi);

// Port Declarations

input [20:0] data_in;
output [20:0] data_out;
input phi;

reg [20:0] data_out;


// latch

always @ (phi or data_in)
begin
  if (phi)
    `LATCH_DELAY data_out <= data_in;
end

endmodule // latch_20bit