chip_snoop.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

`include "definitions.v"



// Produced by /usr/class/ee272/bin/snoopgen from file snoop.in

// Remember to run Verilog with -x if any variables are subscripted


// 2 Clock phases: ext_phi1 ext_phi2
// Input, Verilog: ext_addr_s1, irsim: ext_addr_s1, vector[4:0]
// Input, Verilog: ext_cmd_s1, irsim: ext_cmd_s1, vector[1:0]
// Input, Verilog: ext_phi2, irsim: ext_phi2
// Input, Verilog: ext_phi1, irsim: ext_phi1
// Output, Verilog: valid_out_s1, irsim: valid_out_s1, Stable phase 1
// Inout, Verilog: ext_data_s1, irsim: ext_data_s1, vector[22:20], Stable phase 1
// Inout, Verilog: ext_data_s1, irsim: ext_data_s1, vector[19:0], Stable phase 1


module snooper(
	ext_phi1, ext_phi2, ext_cmd_s1, ext_addr_s1, 
	ext_data_s1, data_mask_io_sel_s1, port_io_sel_s1, 
	valid_out_s1);

input ext_phi1;
input ext_phi2;
input [1:0] ext_cmd_s1;
input [4:0] ext_addr_s1;
input [22:0] ext_data_s1;
input data_mask_io_sel_s1;
input port_io_sel_s1;
input valid_out_s1;

initial
begin
	$rsim_init();
	$rsim_check_on();
end

// One always block per input

always @(ext_addr_s1)
begin
	$rsim_log_input(ext_addr_s1[4], "ext_addr_s1[4]");
	$rsim_log_input(ext_addr_s1[3], "ext_addr_s1[3]");
	$rsim_log_input(ext_addr_s1[2], "ext_addr_s1[2]");
	$rsim_log_input(ext_addr_s1[1], "ext_addr_s1[1]");
	$rsim_log_input(ext_addr_s1[0], "ext_addr_s1[0]");
end
always @(ext_cmd_s1)
begin
	$rsim_log_input(ext_cmd_s1[1], "ext_cmd_s1[1]");
	$rsim_log_input(ext_cmd_s1[0], "ext_cmd_s1[0]");
end
always @(ext_phi2) $rsim_log_input(ext_phi2, "ext_phi2");
always @(ext_phi1) $rsim_log_input(ext_phi1, "ext_phi1");

// One always block per inout

always @(ext_data_s1 or port_io_sel_s1)
	if (port_io_sel_s1 == 0)
	begin
	$rsim_log_input(ext_data_s1[22], "ext_data_s1[22]");
	$rsim_log_input(ext_data_s1[21], "ext_data_s1[21]");
	$rsim_log_input(ext_data_s1[20], "ext_data_s1[20]");
	end
always @(ext_data_s1 or data_mask_io_sel_s1)
	if (data_mask_io_sel_s1 == 0)
	begin
	$rsim_log_input(ext_data_s1[19], "ext_data_s1[19]");
	$rsim_log_input(ext_data_s1[18], "ext_data_s1[18]");
	$rsim_log_input(ext_data_s1[17], "ext_data_s1[17]");
	$rsim_log_input(ext_data_s1[16], "ext_data_s1[16]");
	$rsim_log_input(ext_data_s1[15], "ext_data_s1[15]");
	$rsim_log_input(ext_data_s1[14], "ext_data_s1[14]");
	$rsim_log_input(ext_data_s1[13], "ext_data_s1[13]");
	$rsim_log_input(ext_data_s1[12], "ext_data_s1[12]");
	$rsim_log_input(ext_data_s1[11], "ext_data_s1[11]");
	$rsim_log_input(ext_data_s1[10], "ext_data_s1[10]");
	$rsim_log_input(ext_data_s1[9], "ext_data_s1[9]");
	$rsim_log_input(ext_data_s1[8], "ext_data_s1[8]");
	$rsim_log_input(ext_data_s1[7], "ext_data_s1[7]");
	$rsim_log_input(ext_data_s1[6], "ext_data_s1[6]");
	$rsim_log_input(ext_data_s1[5], "ext_data_s1[5]");
	$rsim_log_input(ext_data_s1[4], "ext_data_s1[4]");
	$rsim_log_input(ext_data_s1[3], "ext_data_s1[3]");
	$rsim_log_input(ext_data_s1[2], "ext_data_s1[2]");
	$rsim_log_input(ext_data_s1[1], "ext_data_s1[1]");
	$rsim_log_input(ext_data_s1[0], "ext_data_s1[0]");
	end

// Let go of inouts

always @(posedge port_io_sel_s1)
begin
	$rsim_update_value("ext_data_s1[22]","x");
	$rsim_update_value("ext_data_s1[21]","x");
	$rsim_update_value("ext_data_s1[20]","x");
end
always @(posedge data_mask_io_sel_s1)
begin
	$rsim_update_value("ext_data_s1[19]","x");
	$rsim_update_value("ext_data_s1[18]","x");
	$rsim_update_value("ext_data_s1[17]","x");
	$rsim_update_value("ext_data_s1[16]","x");
	$rsim_update_value("ext_data_s1[15]","x");
	$rsim_update_value("ext_data_s1[14]","x");
	$rsim_update_value("ext_data_s1[13]","x");
	$rsim_update_value("ext_data_s1[12]","x");
	$rsim_update_value("ext_data_s1[11]","x");
	$rsim_update_value("ext_data_s1[10]","x");
	$rsim_update_value("ext_data_s1[9]","x");
	$rsim_update_value("ext_data_s1[8]","x");
	$rsim_update_value("ext_data_s1[7]","x");
	$rsim_update_value("ext_data_s1[6]","x");
	$rsim_update_value("ext_data_s1[5]","x");
	$rsim_update_value("ext_data_s1[4]","x");
	$rsim_update_value("ext_data_s1[3]","x");
	$rsim_update_value("ext_data_s1[2]","x");
	$rsim_update_value("ext_data_s1[1]","x");
	$rsim_update_value("ext_data_s1[0]","x");
end

// Check stable signals

always @(ext_phi1)
begin
	$rsim_log_output(valid_out_s1, "valid_out_s1");
	if (port_io_sel_s1 == 1)
	begin
	$rsim_log_output(ext_data_s1[22], "ext_data_s1[22]");
	$rsim_log_output(ext_data_s1[21], "ext_data_s1[21]");
	$rsim_log_output(ext_data_s1[20], "ext_data_s1[20]");
	end
	if (data_mask_io_sel_s1 == 1)
	begin
	$rsim_log_output(ext_data_s1[19], "ext_data_s1[19]");
	$rsim_log_output(ext_data_s1[18], "ext_data_s1[18]");
	$rsim_log_output(ext_data_s1[17], "ext_data_s1[17]");
	$rsim_log_output(ext_data_s1[16], "ext_data_s1[16]");
	$rsim_log_output(ext_data_s1[15], "ext_data_s1[15]");
	$rsim_log_output(ext_data_s1[14], "ext_data_s1[14]");
	$rsim_log_output(ext_data_s1[13], "ext_data_s1[13]");
	$rsim_log_output(ext_data_s1[12], "ext_data_s1[12]");
	$rsim_log_output(ext_data_s1[11], "ext_data_s1[11]");
	$rsim_log_output(ext_data_s1[10], "ext_data_s1[10]");
	$rsim_log_output(ext_data_s1[9], "ext_data_s1[9]");
	$rsim_log_output(ext_data_s1[8], "ext_data_s1[8]");
	$rsim_log_output(ext_data_s1[7], "ext_data_s1[7]");
	$rsim_log_output(ext_data_s1[6], "ext_data_s1[6]");
	$rsim_log_output(ext_data_s1[5], "ext_data_s1[5]");
	$rsim_log_output(ext_data_s1[4], "ext_data_s1[4]");
	$rsim_log_output(ext_data_s1[3], "ext_data_s1[3]");
	$rsim_log_output(ext_data_s1[2], "ext_data_s1[2]");
	$rsim_log_output(ext_data_s1[1], "ext_data_s1[1]");
	$rsim_log_output(ext_data_s1[0], "ext_data_s1[0]");
	end
end

always @(ext_phi2)
begin
end


// Check valid signals

always @(negedge ext_phi1)
begin
end

always @(negedge ext_phi2)
begin
end


// Check qualified signals

always @(ext_phi1)
begin
end

always @(ext_phi2)
begin
end



endmodule

//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////


module chip(ext_phi1, ext_phi2, ext_cmd_s1, ext_addr_s1, ext_data_s1, ext_valid_out_s1);

input ext_phi1;
input ext_phi2;
input [1:0] ext_cmd_s1;
input [4:0] ext_addr_s1;
inout [22:0] ext_data_s1;
output ext_valid_out_s1;

wire phi1;                // phase 1 clock driven from pads to core
wire phi2;                // phase 2 clock driven from pads to core
wire [1:0] cmd_s1;        // command to controller
wire [4:0] addr_s1;       // address to controller
wire [22:0] data_in_s1;   // data driven from pads to core
wire [3:0] lsb_addr_q1;   // pre-decoded lsb's of addr ANDed with phi1
wire [4:0] msb_addr_s1;   // pre-decoded msb's of addr
wire cam_wen_q1;          // write (read_b) control line to CAM
wire valid_in_s1;         // valid bit from control to qualify CAM search
wire cam_reset_s1;        // reset bit tells cam when to clear valid bits
wire found_match_v2;      // indicates at least one match in prioritizer
wire addr_sel_s2;         // mux select line for RAM address mux
wire ram_wen_q2;          // write (read_b) control line to RAM
wire data_sel_s1;         // mux select line for output data mux
wire [2:0] no_match_s1;   // port ID to use if !found_match_v2 on search
wire [22:0] data_out_s1;  // data driven from core to pads
wire valid_out_s1;        // stored value of valid bit
wire data_mask_io_sel_s1; // tell data and mask pads to drive or receive
wire port_io_sel_s1;      // tell port pads to drive or receive

wire phi1_b = ~phi1;
wire phi2_b = ~phi2;

datapath datapath(
  phi1_b,
  phi2_b,
  data_in_s1,
  lsb_addr_q1,
  msb_addr_s1,
  cam_wen_q1,
  valid_in_s1,
  cam_reset_s1,
  found_match_v2,
  addr_sel_s2,
  ram_wen_q2,
  data_sel_s1,
  no_match_s1,
  data_out_s1,
  valid_out_s1
);

control control(
  phi1,
  phi2,
  cmd_s1,
  addr_s1,
  data_in_s1[`RAM_DATA],
  lsb_addr_q1,
  msb_addr_s1,
  cam_wen_q1,
  valid_in_s1,
  cam_reset_s1,
  found_match_v2,
  addr_sel_s2,
  ram_wen_q2,
  data_sel_s1,
  no_match_s1,
  data_mask_io_sel_s1,
  port_io_sel_s1
);

pads pads(
  ext_phi1,
  ext_phi2,
  ext_cmd_s1,
  ext_addr_s1,
  ext_data_s1,
  ext_valid_out_s1,
  data_mask_io_sel_s1,
  port_io_sel_s1,
  phi1,
  phi2,
  cmd_s1,
  addr_s1,
  data_in_s1,
  data_out_s1,
  valid_out_s1
);

snooper snooper(
ext_phi1,
ext_phi2,
ext_cmd_s1,
ext_addr_s1,
ext_data_s1,
data_mask_io_sel_s1, 
port_io_sel_s1,
valid_out_s1
);

endmodule // chip