control_1.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

`include "definitions.v"

// Need a Reset signal for reseting all occupied bits of CAM

module control_1(phi1, cmd_s1, addr_s1, funky_addr_s1, lsb_addr_q1, msb_addr_s1,
                 cam_wen_q1, valid_s1, reset_cmd_s1);

input phi1;
input [1:0] cmd_s1;
input [4:0] addr_s1;
output funky_addr_s1;
output [3:0] lsb_addr_q1;
output [4:0] msb_addr_s1; 
output cam_wen_q1;
output valid_s1;
output reset_cmd_s1;

// output variables

wire funky_addr_s1;
reg [3:0] lsb_addr_q1;
reg [4:0] msb_addr_s1;
reg cam_wen_q1;
reg valid_s1;
reg reset_cmd_s1;

// local variables

reg [4:0] msb_addr_tmp_s1;   

// auxiliary signals to generate control signals

assign funky_addr_s1 = (addr_s1 == `FUNKY_ADDR) ? 1'b1 : 1'b0;


// phase 1 control signals

// this block spits out the 5 bits that represent the MSB of the
// CAM wordlines.
always @ (addr_s1)
  begin
     msb_addr_tmp_s1[0] = ~addr_s1[4] & ~addr_s1[3] & ~addr_s1[2];
     msb_addr_tmp_s1[1] = ~addr_s1[4] & ~addr_s1[3] &  addr_s1[2];
     msb_addr_tmp_s1[2] = ~addr_s1[4] &  addr_s1[3] & ~addr_s1[2];
     msb_addr_tmp_s1[3] = ~addr_s1[4] &  addr_s1[3] &  addr_s1[2];
     msb_addr_tmp_s1[4] =  addr_s1[4] & ~addr_s1[3] & ~addr_s1[2];
  end   
   
// this block spits out the 4 bits that represent the LSB of the
// CAM wordlines.  They also come out as q1 signals
// Also: these can be directed to outputs immediately, controller
// will zero the msb lines if no wordlines should be selected
always @ (addr_s1 or phi1)
  begin
     lsb_addr_q1[0] = ~addr_s1[1] & ~addr_s1[0] & phi1;
     lsb_addr_q1[1] = ~addr_s1[1] &  addr_s1[0] & phi1;
     lsb_addr_q1[2] =  addr_s1[1] & ~addr_s1[0] & phi1;
     lsb_addr_q1[3] =  addr_s1[1] &  addr_s1[0] & phi1;
  end
   
always @ (phi1 or cmd_s1 or funky_addr_s1 or msb_addr_tmp_s1)
begin
  case (cmd_s1)
    `WRITE:
      begin
        cam_wen_q1   = 1'b1 & phi1;
        valid_s1     = 1'b1;
        reset_cmd_s1 = 1'b0;
        if (funky_addr_s1) begin
           // writing the no-match port ID
	   msb_addr_s1 = 5'b00000;
        end
        else begin
	   msb_addr_s1 = msb_addr_tmp_s1;
        end
      end
    `SEARCH:
      begin
         cam_wen_q1   = 1'b1 & phi1;
         valid_s1     = 1'b1;
         reset_cmd_s1 = 1'b0;
	 msb_addr_s1 = 5'b00000;
      end
    `READ:
      begin
         cam_wen_q1   = 1'b0 & phi1;
         valid_s1     = 1'b1;  // really don't-care
         reset_cmd_s1 = 1'b0;
         if (funky_addr_s1) begin
           // reading the no-match port ID
	   msb_addr_s1 = 5'b00000;
         end
         else begin
	   msb_addr_s1 = msb_addr_tmp_s1;
         end
      end
    `DELETE:
      begin
         cam_wen_q1   = 1'b1 & phi1;
         valid_s1     = 1'b0;
         if (funky_addr_s1) begin
           // this means reset-- this signal tells the
           // CAM to clear the valid bits and tells our
           // pads to not drive next
           reset_cmd_s1 = 1'b1;
	   // turn off word lines-- CAM valid bits are
           // cleared with sneaky reset signal
	   msb_addr_s1 = 5'b00000;
         end
         else begin
           reset_cmd_s1 = 1'b0;
	   msb_addr_s1 = msb_addr_tmp_s1;
         end
      end
  endcase
end


endmodule // control