📄 tseng.txt
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Tseng Super VGA
ET3000-AX 100pin Max 512k 8/16bit databus, 32bit memory bus. Main chip
-BX 84pin 512k 8 bit databus.
-Bp 256k 8 bit Basic chip
ET4000AX 144pin Max 1M 8/16 bit
ET4000/W32 160pin Max 4MB Accelerator.
ET4000/W32i 160pin Max 4MB Accelerator. Can interleave DRAM
ET4000/W32p 208pin Max 4MB Accelerator, PCI support, point-point Line
draw
Note: W32x means any of W32, W32i and W32p
Registers:
*** ET3000 *****
102h: Microchannel Setup Control
bit 0 Disable Card if set
3B8h (W): Display Mode Control Register
bit 0 80x25. Set for 80x25 text mode, clear for 40x25 text mode
1 Hercules graphics mode if set, text mode else
3 Video enabled if set
5 Blink enabled if set
7 Graphics page 1 displayed if set, page 0 else
3BFh (R/W): Hercules Compatibility Mode
bit 1 Enable second page (B800h-BFFFh)
Note: to enable the Tseng 4000 extensions this register must be written with 3
and then 3d8h must be written with A0h. To disable extensions write 29h
to 3d8h and then 1 to this register.
Extended registers include 3d4h index >18h, except index 33h and 35h
3C0h index 16h: Miscellaneous
bit 0 If set disables writes to bits 0-3 of the Overscan (3C0h index 11h)
register.
1 If set disables writes to Internal/External Palette RAM.
4 If set the Horizontal Timings (3d4gh index 0-5), CRTC Offset (3d4h
index 13h) and Display Start Address (3d4h index 0Ch,0Dh) are doubled
(or more correctly: the units they are specified in are doubled).
6 If set enables 2byte character codes
7 Ignore EGA internal palette if set
3C0h index 17h (R/W): Miscellaneous 1
bit 7 If set protects the internal palette ram and redefines the attribute
bits as follows:
Monochrome:
bit 0-2 Select font 0-7
3 If set selects blinking
4 If set selects underline
5 If set prevents the character from being displayed
6 If set displays the character at half intensity
7 If set selects reverse video
Color:
bit 0-1 Selects font 0-3
2 Foreground Blue
3 Foreground Green
4 Foreground Red
5 Background Blue
6 Background Green
7 Background Red
3C3h (R/W): Microchannel Video Subsystem Enable Register:
bit 0 Enable Microchannel VGA if set
3C4h index 6 (R/W): Zoom Control
bit 0-2 Yzoom factor 0=x1, 1: x2 .... 7: x8
4-6 Xzoom factor 0=x1, 1: x2 .... 7: x8
7 Hardware zoom enabled if set
3C4h index 7 (R/W): TS Auxiliary Mode
bit 0 Switch Normal Window if set. Switches the normal window to text mode if
programmed for graphics mode, and vice versa.
1 Switch Zoom Window if set. Switches the zoom window to text mode if
programmed for graphics mode, and vice versa.
2 Switch Split Window if set. Switches the spilt window to text mode if
programmed for graphics mode, and vice versa.
4 If set 8 simultaneous fonts are enabled, using bit 3,4,6 of each
attribute byte to select the font.
3,5 ROM Bios Enable/Disable:
0 0 C000-C3FF Enabled
0 1 ROM disabled (-AX), C000-C5FFF (-AF)
1 0 C000-C5FF,C680-C7FF Enabled
1 1 C000-C7FF Enabled
6 MCLK/2 if set
7 VGA compatible if set, EGA if clear.
3CBh (R/W): PEL Address/Data Wd (3000/4000 ?)
3CDh (R/W): Segment Select
bit 0-2 64k Write bank number
3-5 64k Read bank number
6-7 Segment Configuration.
0 128K segments
1 64K segments
2 1M linear memory
3CEh index 0Dh (R/W): Microsequencer Mode
3CEh index 0Eh (R/W): Microsequencer Reset
3d4h index 1Bh (R/W): X Zoom Start Address
bit 0-7 Offset of Zoom window start in character clocks (8 pixels) from left
edge. The horizontal zoom area (End - Start) should be an integral
(positive) multipla of the horizontal zoom factor
3d4h index 1Ch (R/W): X Zoom End
bit 0-7 Offset of Zoom window end in char clocks from left edge
3d4h index 1Dh (R/W): Y Zoom Start Address
bit 0-7 Start line of zoom window bit 0-7
3d4h index 1Eh (R/W): Y Zoom End Address
bit 0-7 End line of zoom window bit 0-7. This is the last line to be zoomed.
3d4h index 1Fh (R/W): Y Zoom Start and End High
bit 0-2 End line of zoom window bit 8-10. Bits 0-7 are in index 1Eh
3-5 Start line of zoom window bit 8-10. Bits 0-7 are in index 1Dh
3d4h index 20h (R/W): Zoom Start Address Low
bit 0-7 Zoom Start Address bit 0-7. Address of the data to be zoomed in the
zoom window
3d4h index 21h (R/W): Zoom Start Address Middle
bit 0-7 Zoom Start Address bit 8-15
3d4h index 23h (R/W): Extended start ET3000
bit 0 Cursor start address bit 16
1 Display start address bit 16
2 Zoom start address bit 16
7 If set memory address 8 is output on the MBSL pin (allowing access to
1MB), if clear the blanking signal is output.
3d4h index 24h (R/W): Compatibility Control
bit 0 Enable Clock Translate if set
1 Clock Select bit 2. Bits 0-1 are in 3C2h/3CCh.
2 Enable tri-state for all output pins if set
3 Enable input A8 of 1MB DRAMs from the INTL output if set
4 Reserved
5 Enable external ROM CRTC translation if set
6 Enable Double Scan and Underline Attribute if set
7 Enable 6845 compatibility if set.
3d4h index 25h (R/W): Overflow High
bit 0 Vertical Blank Start bit 10
1 Vertical Total Start bit 10
2 Vertical Display End bit 10
3 Vertical Sync Start bit 10
4 Line Compare bit 10
5-6 Reserved
7 Vertical Interlace if set
3D8h (W): Mode Control register
bit 0 80x25 Alpha mode if set, 40x25 else
1 Graphics mode if set, alpha else.
2 BW mode if set, color else
3 Video Enable. Enable video signal if set
4 640x200 Graphics mode if set, 320x200 else
5 if set bit 7 of the attribute controls background, else blink
3D9h (W): Color Select Register
The function of this register depends on the active mode.
Text modes: 320x200 modes: 640x200 mode:
Bit 0 Blue border Blue background Blue ForeGround
1 Green border Green background Green ForeGround
2 Red border Red background Red ForeGround
3 Bright border Bright background Bright ForeGround
4 Backgr. color Alt. intens. colors Alt. intens colors
5 No func. Selects palette
Palette 0 is Green, red and brown,
Palette 1 is Cyan, magenta and white.
3dAh (W): Feature Control Register
bit 5 (R) Hercules Compatibility Register (3BFh) bit 1
7 Enable NMI generation if set
Note: Read at 3CAh, Written at 3dAh
Note: Bits 0,1 and 3 are standard EGA/VGA
3DEh (W); AT&T Mode Control Register
bit 0 Set to double scanlines (200 -> 400)
2 Alternate Font Select.
3 Alternate Page Select. If bit 0 is clear, selects the 16KB page to
display from
6 Underline Color Attribute. If set text with underline attribute is
shown with the white underline, if clear it is shown in blue
foreground color
Note: To update this register the system must be in color mode (3CCh bit 0
set) and 3d4h index 34h bits 6 and 7 must be set as follows:
bit 0 3d4h index 34h bits 7 must be set
2,3 3d4h index 34h bits 7 must be set
6 3d4h index 34h bits 6 must be set
*** Tseng ET4000AX and ET4000/W32 variants
102h: Microchannel Setup Control
bit 0 Disable Card if set
3BFh (R/W): Hercules Compatibility Mode
bit 1 Enable second page (B800h-BFFFh)
Note: to enable the Tseng 4000 extensions this register must be written with 3
and then 3d8h must be written with A0h. To disable extensions write 29h
to 3d8h and then 1 to this register.
Extended registers include 3d4h index >18h, except index 33h and 35h
3C0h index 16h: Miscellaneous
bit 0 If set disables writes to bits 0-3 of the Overscan (3C0h index 11h)
register.
1 If set disables writes to Internal/External Palette RAM.
4,5 (4000) High resolution timings.
0: Normal powerup mode
2: Hiresolution 256color mode
3: 15/16 bit HiColor mode (bytes on rising AND falling edge
of the dot clock)
(W32x) High Resolution /color mode
0: Normal 8bits/clock
2: 16bits per clock (HiColor)
6 If set enables 2byte character codes
7 Ignore EGA internal palette if set
3C0h index 17h (R/W): Miscellaneous 1
bit 7 If set protects the internal palette RAM and redefines the attribute
bits as follows:
Monochrome:
bit 0-2 Select font 0-7
3 If set selects blinking
4 If set selects underline
5 If set prevents the character from being displayed
6 If set displays the character at half intensity
7 If set selects reverse video
Color:
bit 0-1 Selects font 0-3
2 Foreground Blue
3 Foreground Green
4 Foreground Red
5 Background Blue
6 Background Green
7 Background Red
3C3h (R/W): Microchannel Video Subsystem Enable Register:
bit 0 Enable Microchannel VGA if set
3C4h index 6 (R/W): TS State Control
bit 1-2 Font Width Select in dots/character
If 3C4h index 4 bit 0 clear:
0: 9 dots, 1: 10 dots, 2: 12 dots, 3: 6 dots
If 3C4h index 5 bit 0 set:
0: 8 dots, 1: 11 dots, 2: 7 dots, 3: 16 dots
Only valid if 3d4h index 34h bit 3 set.
3C4h index 7 (R/W): TS Auxiliary Mode
bit 0 Selects MCLK/4 as video clock if set (bit 6 must be set)
1 Selects SCLK=MCLK
2 (4000) Always 1
2,4 (W32x) CRTC Horizontal Scale Factor. The number of times each pixel is
replicated horizontally. 0: x8, 1: x4, 2: x2, 3: x8
3,5 ROM Bios Enable/Disable:
0 0 C000-C3FF Enabled
0 1 ROM disabled
1 0 C000-C5FF,C680-C7FF Enabled
1 1 C000-C7FF Enabled
6 MCLK/2 if set and bit 0 is 0
7 VGA compatible if set, EGA if clear.
3CBh (R/W): PEL Address/Data Wd (3000/4000 ?)
3CBh (R/W): Extended bank register (W32 only)
bit 0-1 Write bank bit 4-5. The lower 4 bits are in 3CDh bit 0-3.
4-5 Read bank bit 4-5. The lower 4 bits are in 3CDh bit 4-7.
3CDh (R/W): Segment Select
bit 0-3 64k Write bank number (0..15)
4-7 64k Read bank number (0..15)
3CEh index 0Dh (R/W): Microsequencer Mode
3CEh index 0Eh (R/W): Microsequencer Reset
3d4h index 30h (R/W): (W32x ?)
bit 0-? Linear Frame Buffer Address in units of 4Mb
3d4h index 31h (R/W): General Purpose
bit 0-3 Scratch pad
3 (W32p?) 1280x1024 frequency: 0: 43Hz i-lace, 1: 60Hz
6-7 Clock Select bits 3-4. Bits 0-1 are in 3C2h/3CCh bits 2-3.
3d4h index 32h (R/W): RAS/CAS Configuration
bit 0-1 CAS low Pulse Width (Tcsw). The CAS low pulse width in SCLK cycles.
For graphics modes and the CAS0,CAS1 signals in text mode the period
is 2 SCLK cycles if this value is 1, 1 SCLK cycle if not.
For the CAS2 and CAS3 signals in text mode the period is:
0: 1 SCLK cycle, 1: 2, 2: 3, 3: 4
2 CAS Pre-charge Time (Tcsp). The CAS high pulse width is 1 SCLK cycle
if clear, 2 if set
3-4 RAS Pre-charge Time (Trsp). The RAS high pulse width in SCLK cycles
0: 2 SCLK cycles, 1: 3, 2: 4, 3: 5
5 Recharge time (Trcd). If set Trcd is 3 SCLK cycles, if clear only 2
6 RAL RAS & CAS Column Setup Time (Tral).
7 (W32i/p) Set if using interleaved memory.
3d4h index 33h (R/W): Extended start Address
bit 0-1 (4000) Display Start Address bits 16-17
2-3 (4000) Cursor start address bits 16-17
Can be used to ID ET4000
0-3 (W32x) Display Start Address bits 16-19. Bits 0-15 are in 3d4h index
0Ch,0Dh
4-7 (W32x) Cursor Start Address bits 16-19. Bits 0-15 are in 3d4h index
0Eh,0Fh
Note: This register can be accessed whether or not the extensions are enabled
3d4h index 34h (R/W): 6845 Compatibility Control Register
bit 0 Enable CS0 (alternate clock timing)
1 Clock Select bit 2. Bits 0-1 in 3C2h bits 2-3, bits 3-4 are in 3d4h
index 31h bits 6-7
2 Tristate ET4000 bus and color outputs if set
3 Video Subsystem Enable Register at 46E8h if set, at 3C3h if clear.
4 Enable Translation ROM for reading CRTC and MISCOUT if set
5 Enable Translation ROM for writing CRTC and MISCOUT if set
6 Enable double scan in AT&T compatibility mode if set
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