tseng.txt
来自「比较详尽的VGA端口寄存器的文档」· 文本 代码 · 共 968 行 · 第 1/3 页
TXT
968 行
4-6 Source Y Wrap. The Source Map will wrap back to the start when
this number of lines have been processed.
0: 1 line, 1: 2 lines, 2: 4 lines, 3: 8 lines, 7: never
M+94h W(R/W): ACL X Position Register (W32,W32i only)
bit 0-11 The accelerators current X position
Note this register is at offset 38h in the W32p
M+96h W(R/W): ACL Y Position Register (W32,W32i only)
bit 0-11 The accelerators current Y position
Note this register is at offset 3Ah in the W32p
M+98h W(R/W): ACL X Count Register
bit 0-11 The number of bytes (-1) in the blit area horizontally. For 15/16/24
bpp modes the number of bytes is the number of pixels * 2/3/4
depending on the mode.
M+9Ah W(R/W): ACL Y Count Register
bit 0-11 The number of lines (-1) in the blit area vertically
M+9Ch (R/W): ACL Routing Control Register
bit 0-2 Routing of CPU Data (DARO).
0: CPU data not used
1: CPU data is Source data
2: CPU data is Mix data
4: CPU data is X Count
5: CPU data is Y Count
3 (W32p) MixMap Enable (MXEN). If set mixed data is display data, if
clear mixed data is 1. Only used if bits 0-2 are 0 or 1.
4-5 Routing of CPU Address (ADRO).
0: CPU address not used. Only the first write to an accelerated
MMU Aperture is used as the destination address
1: CPU address is Destination address
6 (W32p) Routing of Accelerator data.
7 (W32p) Invalidate disable
M+9Dh (R/W): ACL Reload Control Register
bit 0 If set the resulting Source Address from the last operation is used
as the new starting Source Address, if clear the address programmed
in the ACL Source Address Register (M+84h).
1 If set the resulting Pattern Address from the last operation is used
as the new starting Pattern Address, if clear the address programmed
in the ACL Pattern Address Register (M+80h).
M+9Eh (R/W): ACL Background Raster Operation Register
bit 0-7 The Background Raster Operation
M+9Fh (R/W): ACL Foreground Raster Operation Register
bit 0-7 The Foreground Raster Operation
M+A0h D(R/W): ACL Destination Address Register
bit 0-21 The byte address in display memory of the Destination Map
The Destination address can also be set by writing via a MMU
Aperture with the APT bit set. Then the address (after MMU
translation) is used as the Destination address and the Accelerator
operation is started. Reading this register returns the accelerator
internal Destination address
M+A4h D(R): ACL Internal Pattern Address Register (W32,W32i only)
bit 0-21 The accelerator internal Pattern Address
M+A4h D(R): ACL Mix Address Register (W32p rev A & B only)
bit 0-24 Address of the Mix map in display memory. The Mix map has one bit
for each byte processed by any other map
M+A8h D(R): ACL Internal Source Address Register (W32,W32i only)
bit 0-21 The accelerator internal Source Address
M+A8h W(R): ACL Mix Y Offset Register (W32p only)
bit 0-11 Number of bits (-1) per scan line in the Mix map.
M+AAh W(R): ACL Error Term Register (W32p only)
bit 0-15 Bresenham linedraw error term. Only used if ACL X/Y Direction
Register (M+8Fh) bit 5 is set. Usually this is automatically
calculated from the ACL Delta Major register (M+AEh), however for
restoring a suspended operation or for clipping of the line this
register can be used for direct control.
M+ACh W(R/W): ACL Delta Minor (W32p only)
bit 0-? Bresenham linedraw length of the minor axis. min(abs(dX),abs(dY))
M+AEh W(R/W): ACL Delta Major (W32p only)
bit 0-? Bresenham linedraw length of the major axis. max(abs(dX),abs(dY))
Where dX and dY are the distances in the X and Y directions.
**** The PCI Interfece registers are only present on the W32p ****
Byte 00h W(R): Vendor ID
bit 0-15 100Ch for Tseng Labs
Byte 02h W(R): Device ID
bit 0-3 Revision ID. Same as 210Ah index ECh bits 4-7. Also same as Byte 8.
4-15 Device ID. 320h for all ET4000/W32p's
Byte 04h W(R/W): Command Register
bit 0 I/O Space. If set the device may respond to I/O accesses
1 Memory Space. If set the device may respond to memory accesses
2 Reserved(0)
3 Special cycles. If set the device is allowed to monitor special
cycles
4 Reserved(0)
5 VGA Palette snoop. If set VGA palette snooping is enabled and the
DAC can not respond to writes. If clear the DAC operates normally
6 Parity error. If set the device responds to parity errors, if clear
they are ignored. Must be reset to 0. The device will (and must)
generate parity even when parity errors are disabled.
7 Wait cycle control. If set address/data stepping is enabled
8 System error driver. If set the system error driver reports parity
errors, if clear it is disconnected.
9 Reserved(0)
Byte 06h W(R/W): Device Status Register
bit 8 Bus Master
9-10 (R) Device Select Timing. Timing of DEVSEL#. 0: fast, 1: medium,
2: slow
11 Device Target-abort.
Note: The bits are set when the corresponding event occurs, and are reset when
a one (1) is written to the bit.
Byte 08h (R): Revision ID
bit 0-7 Revision ID. Same as 210Ah index ECh bits 4-7. Also same as Byte 2
bits 0-3.
Byte 09h 3(R): Class Code
bit 0-23 30000h for a VGA compatible display controller
Byte 10h D(R/W): Base Address Register
bit 24-31 Selects the 16MB area where the Linear Aperture resides (A24-31 =
these bits) when enabled.
Byte 30h D(R/W): Expansion ROM Address
bit 0 If set the ROM is enabled, if clear it is disabled
1-27 Reserved(0)
28-31 (rev A,B) Reserved (0)
(rev C +) Selects the 256MB area where the ROM resides (A28-31 =
these bits).
Note: when bit 1-31 is 0 the ROM is at C0000h, else it is replicated every 32K
within the 256MB area (if enabled).
Byte 3Ch (R/W): Interrupt Line
bit 0-3 (rev A) Reserved (all 1)
(rev B +) Input to the system interrupt controller ??
4-7 (rev A,B) Reserved (all 1)
(rev C +) Reserved (0)
Byte 3Dh (R): Interrupt Pin
Bank Switching:
64k banks are selected by the Segment Select Register at 3CDh.
Both a Read and a Write segment can be selected.
For the W32 series extra bank bits are in 3CBh
Hardware Zoom (ET3000 Only).
The ET3000 can zoom a part of display memory in a window.
The display memory position and window position are selected by 3d4h index
1Bh to 21h.
Identify Tseng Chipset:
outp($3BF,3);
outp($3D8,$A0); {Enable ET4000 extensions}
if tstrg($3CD,$3F) then
if testinx2(base,$33,$F) then
if tstrg($3CB,$33) then
case rdinx($217A,$EC) shr 4 of
0:Tseng ET4000W32
3:Tseng ET4000W32i
2:Tseng ET4000W32p {Not quite sure yet}
end
else Tseng 4000
else Tseng 3000;
Memory: (Tseng BIOS version 3.00 and up)
0:488h BYTE Bit 4 High bit of the 1024x768 mode flag
0: 87Hz interlaced, 1: 60Hz, 2: 72Hz, 3: 70Hz
5 High bit of 800x600 mode flag
0: 60Hz, 1: 56Hz, 2: 72Hz
6 If set 640x480 is 72Hz, else 60Hz
0:489h BYTE Bit 5 Low bit of the 1024x768 mode flag
6 Low bit of the 800x600 flag
Video Modes:
8 T 132 25 2 (STB only)
Ah T 132 44 2
18h T 132 44 4 (8x8) B000
19h T 132 25 4 (9x14) B000
1Ah T 132 28 4 (9x13) B000
22h T 132 44 16 (8x8)
23h T 132 25 16 (8x14)
24h T 132 28 16 (8x13)
25h G 640 480 16 planar
26h T 80 60 16 (8x8)
27h G 720 512 16 PL4 (Tseng recommended, few boards)
29h G 800 600 16 PL4
2Ah T 100 40 16 PL4
2Dh G 640 350 256 P8
2Eh G 640 480 256 P8
2Fh G 640 400 256 P8 (ET4000 Only)
2Fh G 720 512 256 P8 (Tseng recommended, few boards)
30h G 800 600 256 P8
36h G 960 720 16 PL4 (STB only)
37h G 1024 768 16 PL4
38h G 1024 768 256 P8 (ET4000 Only)
3Dh G 1280 1024 16 PL4 (newer ET4000s)
3Eh G 1280 960 16 PL4 (Definicon)
3Fh G 1280 1024 256 P8
6Ah G 800 600 16 PL4 Newer ET4000s
BIOS extensions (Tseng 4000 Sierra HiColor DAC):
----------1010E0-----------------------------
INT 10 - VIDEO - SpeedStar 24 - Set TrueColor Graphics Mode
AX = 10E0h
BL = 2Eh
Return: AX = 0010h if successful
other on error
Enters 24bit 640x480 mode if SS24 DAC present.
Video memory is NOT cleared.
Each line uses 2048 bytes with only 640x3=1920 bytes actually used.
So that a line can never cross a 64K border.
----------1010F0-----------------------------
INT 10 - VIDEO - Tseng ET-4000 BIOS - Set HiColor Graphics Mode
AX = 10F0h
BL = video mode (see also AH=00h)
32768-color modes:
13h = 320x200
2Dh = 640x350
2Eh = 640x480
2Fh = 640x400
30h = 800x600
38h = 1024x768
16M color modes:
3Eh = 640x480 (Genoa 7900)
BX = 2DFFh = 640x350 (MEGAVGA/2)
2EFFh = 640x480 (MEGAVGA/2)
2FFFh = 640x400 (MEGAVGA/2)
Return: AX = 0010h if successful
other on error
----------1010F1-----------------------------
INT 10 - VIDEO - Tseng ET-4000 BIOS - GET DAC TYPE
AX = 10F1h
Return: AX = 0010h if successful, errorcode if not
BL = type of digital/analog converter
00h normal VGA DAC
01h Sierra SC11481/6/8 HiColor DAC
(Diamond SpeedStar 24:)
02h SS24 DAC (MUSIC MU9c1880)
(Tseng generic BIOS rev 8.00 or later:)
02h Sierra Mark2 (15-bit) or Mark3 (15/16-bit) DAC
03h ATT20c490/1/2 & Winbond 490/491 15/16/24 bit HiColor DAC
04h AcuMos ADAC1 & CL-GD5200 (15/16/24 bit)
05h Sierra SC15025/26 (15/16/24 bit DAC)
06h Cirrus Internal 15/16/24 bit DAC (from CL-GD54xx series).
07h Diamond SS2410 & MUSIC MU9C1880. (15/16/24 bit).
08h Music MU9c4910/9910 (15/16/24 bit DAC).
09h Brooktree Bt481/482
20h SGS-Thompson STG1700
21h SC15021
22h AT&T 20c498
23h ICS 5340/5341
24h STG1702/3
25h Chrontel CH8398
----------1010F2-----------------------------
INT 10 - VIDEO - Tseng ET-4000 BIOS - GET/SET HiColor MODE
AX = 10F2h
BL = 00h Get current HiColor mode
01h Set 15bit HiColor mode
02h Set 16bit HiColor mode
Return: AX = 0010h if successful, errorcode if not
BL = Current HiColor mode:
00h Not in HiColor mode or not a HiColor DAC
01h 15-bit RGB mode
02h 16-bit RGB mode
03h 24-bit RGB mode
Note: Set HiColor mode (BL=1 or 2) only works if already in some HiColor mode.
----------101D-------------------------------
INT 10 - VIDEO - SpeedSTAR Plus BIOS v4.23+ - SET SYNC PARAMETERS
AH = 1Dh
AL = Video Mode
ES = Caller's segment
Note: The caller's segment contains a table at offset 5Ch or 100h
Offset Size Description
00h 9 BYTEs ID string 'ey5CENTER'
09h 5 BYTEs sync parameters for 640x480 modes 11h,12h,25h,26h,2Eh
0Eh 5 BYTEs sync parameters for 800x600 modes 29h,30h,2Ah
13h 5 BYTEs sync parameters for 1024x768 modes 37h, 38h
----------101DAA-----------------------------
INT 10 - VIDEO - Diamond SpeedSTAR - CHECK FOR SPEEDSTAR
AX = 1DAAh
BX = FDECh
Return: BX = DECFh if found
AL = AH = DACtype:
00h Standard VGA DAC
01h Highcolor DAC with command bit 3 not writable
(Sierra "Mark 1" - SC11481/6/8)
02h SS2410 DAC
05h Highcolor DAC with command bit 3 writable (Sierra
"Mark 2/3" - SC11482/3/4/5/7/9)
SI:DI -> BIOS version & Copyright string
Notes:
The sequence:
port[$3BF]:=3;
port[$3D8]:=$A0;
is needed to enable the extensions in the Tseng 3000/4000.
Most BIOSes do this by default, but some such as the Sigma VGA Legend
requires this sequence.
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?