tseng.txt
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7 Enable 6845 compatibility if set
3d4h index 35h (R/W): Overflow High
bit 0 Vertical Blank Start Bit 10 (3d4h index 15h).
1 Vertical Total Bit 10 (3d4h index 6).
2 Vertical Display End Bit 10 (3d4h index 12h).
3 Vertical Sync Start Bit 10 (3d4h index 10h).
4 Line Compare Bit 10 (3d4h index 18h).
5 Gen-Lock Enabled if set (External sync)
6 (4000) Read/Modify/Write Enabled if set. Currently not implemented.
(W32x) If set selects the CRTCB or Sprite registers as the source
for Vertical Retrace Interrupts, if clear selects the
standard CRTC registers
7 Vertical interlace if set. The Vertical timing registers are
programmed as if the mode was non-interlaced!!
3d4h index 36h (R/W): Video System Configuration 1
bit 0-2 Refresh count. Number (-1) of refreshes per display line
3 (4000) 16 bit wide fonts if set, else 8 bit wide
(W32x) If set enables the Memory Management buffers
4 Linear addressing if set
(4000) Video Memory is mapped as a 1 Meg block above 1MB.
(W32x) Video Memory is mapped as a 4MB block
5 ? Enable Tseng Addressing Mode
(W32x) If set enables Memory Mapped registers. Three MMU areas
exist. All accesses to these areas will be translated by the MMU
to find the resulting address in display memory (or if the access
is to the Accelerator data buffers). The translation happens by
adding the offset into the MMU area to the MMU base address.
In the standard VGA graphics modes (A0000h-AFFFFh VGA buffer) the
area B8000h-B9FFFh is MMU area 0, BA000h-BBFFFh is MMU area 1 and
BC000h-BDFFFh is MMU area 2.
6 16 bit data path (video memory) if set
7 16 bit data (I/O operations) if set
Note: Access to video memory, the MMU buffers and the Memory Mapped registers
are controlled by bits 3-5, 3CEh index 6 bits 2-3 (MAP) and whether the
IMA port is enabled:
Bits MMU
3 5 4 MAP VGA mem MMU 0-2 Size Mem. Regs
0 0 0 0 A0000h- BFFFFh
0 0 0 1 A0000h- AFFFFh
0 0 0 2 B0000h- B7FFFh
0 0 0 3 B8000h- BFFFFh
1 0 0 0 A0000h- BFFFFh
1 0 0 1 A0000h- AFFFFh B8000h- BDFFFh 8K
1 0 0 2 B0000h- B7FFFh A8000h- ADFFFh 8K
1 0 0 3 B8000h- BFFFFh A8000h- ADFFFh 8K
1 1 0 0 A0000h- BFFFFh
1 1 0 1 A0000h- AFFFFh B8000h- BDFFFh 8K BFF00h- BFFFFh
1 1 0 2 B0000h- B7FFFh A8000h- ADFFFh 8K AFF00h- AFFFFh
1 1 0 3 B8000h- BFFFFh A8000h- ADFFFh 8K AFF00h- AFFFFh
IMA port enabled:
0 0 1 0 00000h-0FFFFFh
1 1 1 0 00000h-07FFFFh 080000h-0DFFFFh 128K 0FFF00h-0FFFFFh
IMA port not enabled
0 0 1 0 00000h-3FFFFFh
1 1 1 0 00000h-1FFFFFh 200000h-37FFFFh 512K 3FFF00h-3FFFFFh
Note: If Memory Mapped Registers are enabled (bit 5 set) The addresses
following the last MMU aperture appears to be mapped to "External Mapped
Registers". The size of this area is half the MMU size, I.e for the
standard VGA graphics mode (A0000h-AFFFFh VGA buffer) the External
Mapped Registers would be in the area: BE000h-BEFFFh
3d4h index 37h (R/W): Video System Configuration 2
bit 0-1 (4000) Bus width (VGA chip to video memory):
1: 8 bit, 2: 16 bit, 3: 32 bit.
0 (W32x) Bus Width (VGA chip to video memory) 0: 16bit, 1: 32bit
2 (4000) Bus Read Latch control (0: Delay one clock before latching)
(W32x) If set the CAS signals are output on the CAS0-3 pins and the
Write Enable signals are output on the MWA and MWB pins.
If clear this is reversed.
3 (4000) Size of RAM chips. 0: 64Kx, 1: 256Kx
(W32x) Size of RAM chips. 0: 1Mx, 1: 256Kx (or 512Kx)
RAM size is (Chip size 64k/256k/1M) * (Bus Width 1/2/4 bytes)
For W32i/p multiply with 2 if interleaved (index 32h bit 7 set).
Note: Probably doesn't work for 512Kx DRAMs
4 16 bit ROM access if set, if clear 32bit in Local Bus systems, 8bit
for ISA and MicroChannel systems.
5 Priority Threshold Control. If clear increases the Memory bandwidth
but also increases the response time.
6 Enable test mode if set, should be clear
7 (4000) VRAM installed if set, DRAM if clear.
3d4h index 3Fh (R/W):
bit 0 Bit 8 of the Horizontal Total (3d4h index 0)
2 Bit 8 of the Horizontal Blank Start (3d4h index 3)
4 Bit 8 of the Horizontal Retrace Start (3d4h index 4)
7 Bit 8 of the CRTC offset register (3d4h index 13h).
3DEh (W); AT&T Mode Control Register
bit 0 Set to double scanlines (200 -> 400)
2 Alternate Font Select
3 Alternate Page Select. If bit 0 is clear, selects the 16KB page to
display from
6 Underline Color Attribute. If set text with underline attribute is
shown with the white underline, if clear it is shown in blue
foreground color
Note: To update this register the system must be in color mode (3CCh bit 0
set) and 3d4h index 34h bits 6 and 7 must be set as follows:
bit 0 3d4h index 34h bits 7 must be set
2,3 3d4h index 34h bits 7 must be set
6 3d4h index 34h bits 6 must be set
3d8h (R/W): Display Mode Control
**** The memory mapped registers and index registers at 21xAh are only
present on the ET4000/W32 series chips, not on the ET3000 and ET4000s ****
21xAh index E0h W(R/W): CRTCB/Sprite Horizontal Pixel Position
bit 0-11 The X position of the HardWare Cursor/CRTCB window in pixels from
the left edge of the display
Note: The CRTCB/Sprite&IMA registers are at index 21xAh, where x is 0..7.
The index used by the chip is determined on powerup by the powerup/down
resistors tied to pin IOD0-2. All systems I have seen uses 217Ah.
Note: The E0h-EFh indexes holds either the CRTCB or the Sprite (Cursor)
parameters depending on index EFh bit 0
21xAh index E2h W(R/W): CRTCB Width/Sprite Horizontal Preset
bit 0-11 (CRTCB) The width in pixels (-1) of the CRTCB window
0-5 (Sprite) The pixel number (from the left) within the 64x64 cursor
bitmap of the first used pixel. The last pixel displayed is the 63th
pixel in the bitmap.
21xAh index E4h W(R/W): CRTCB/Sprite Vertical Pixel Position
bit 0-11 The Vertical position of the CRTCB Window/Sprite (Cursor) in
scanlines from the top of the display
21xAh index E6h W(R/W): CRTCB Height/Sprite Vertical Preset
bit 0-11 (CRTCB) The height in scanlines (-1) of the CRTCB window
0-5 (Sprite) The pixel number (from the top) within the 64x64 cursor
bitmap of the first used pixel. The last line displayed is line 63
of the bitmap.
21xAh index E8 3(R/W): CRTCB/Sprite Starting Address
bit 0-19 The address in Video Memory of the start of the CRTCB/Sprite
(Cursor) BitMap.
In bytes in planar modes, and in DWORDs in packed modes.
Note: The sprite data is a 64x64 2bit bitmap
0: Sprite Color 0
1: Sprite Color 1
2: Transparent
21xAh index EBh W(R/W): CRTCB/Sprite Row Offset
bit 0-11 Width of the each CRTCB/Sprite (Cursor) scanline. Should be 4 for
Sprite data. For the CRTCB window it is in bytes in planar modes and
DWORDs in packed modes
12-15 (R) Chip version. 0: W32, 1: W32i revA, 2: W32p revA, 3: W32i revB,
5: W32p revB, 6: W32p revD, 7: W32p rev C, 11: W32i rev C
21xAh index EDh (R/W): CRTCB Pixel Panning
bit 0-2 Number of pixels to shift the CRTCB data left
21xAh index EEh (R/W): CRTCB Color Depth
bit 0-3 The color depth (bits/pixel) of the CRTCB window data
0: 1bit/pixel, 1: 2b/p, 2: 4b/p, 3: 8b/p, 4: 16b/p
4-5 CRTCB Horizontal Zoom Factor. 0: x1, 1: x2, 2: x3, 3: x4
6-7 CRTCB Vertical Zoom Factor. 0: x1, 1: x2, 2: x3, 3: x4
21xAh index EFh (R/W): CRTCB/Sprite Control
bit 0 If set selects the CRTCB window, if clear selects the Sprite
1 If set the CRTCB/Sprite is overlayed on the screen data, if clear it
is output on the SP0-1 pins
2 Sprite Size. 0: 64x64, 1: 128x128
Note: 21xAh index F7h bit 7 must be set to enable the CRTCB window or the
Sprite (Cursor).
21xAh index F0h 3(R/W): Image Starting Address
bit 0-19 Image port Storage address. In bytes in planar modes and in DWORDs
in packed modes. The data input from the IMA port is stored at this
address, starting anew for each frame
21xAh index F3h W(R/W): Image Transfer Length
bit 0-11 The number of DWORDs to transfer per scan line
21xAh index F5h W(R/W): Image Row Offset
bit 0-11 The number of DWORDs from the start of one scanline to the start of
the next scan line.
21xAh index F7h (R/W): Image Port Control
bit 0 Set to enable the Image Port
1 Set to enable odd/even interlace transfers, clear for linear
transfers
7 Set to enable the CRTCB window or the HardWare Cursor (Sprite).
46E8h (R): Video Subsystem Enable Register
bit 3 Enable VGA if set
M+00h D(R/W): MMU Memory Base Pointer Register 0
bit 0-21 The address in display memory where MMU Aperture 0 starts in bytes
M+04h D(R/W): MMU Memory Base Pointer Register 1
bit 0-21 The address in display memory where MMU Aperture 1 starts in bytes
M+08h D(R/W): MMU Memory Base Pointer Register 2
bit 0-21 The address in display memory where MMU Aperture 2 starts in bytes
M+13h (R/W): MMU Control Register
bit 0 If set accesses via MMU Aperture 0 go to the Accelerator registers
1 If set accesses via MMU Aperture 1 go to the Accelerator registers
2 If set accesses via MMU Aperture 2 go to the Accelerator registers
4 If set the memory accessed via MMU Aperture 0 is organised linearly
(As if 3C4h index 2 bits 0-3 = 0Fh, 3C4h index 4 bit 3 = 1, 3CEh
index 1 bits 0-3 = 0, 3CEh index 3 bits 0-4 = 0, 3CEh index 5 bits
0-1 and 3 = 0, 3CEh index 6 bit 1 = 0 and 3CEh index 8 = 0FFh),
if clear the memory is organised according to the current display
mode
5 Same as bit 4, but for MMU Aperture 1
6 Same as bit 4, but for MMU Aperture 2
M+30h (R/W): ACL Suspend/Terminate Register
bit 0 To suspend an Accelerator operation the programmer should set this
bit, wait for the ACL Status Register (Memory 36h) bit 0 to clear
and then clear this bit.
4 Same as bit 0, bit terminates the operation.
M+31h (W): ACL Operation State Register
bit 0 When set the contents of the Queued registers (Memory 80h-FFh) are
transfered to the accelerators internal registers
3 When set a paused screen-to-screen operation is resumed.
4 Should be set on startup for the W32p ??
M+32h (R/W): ACL Sync Enable Register
bit 0 If set a write to a "full" queue (Ie. the queued registers are being
transferred to the internal registers) will be delayed until the
transfer has completed, if clear the write will be ignored. An
interrupt can be generated in this situation.
M+33h (R?): ACL Write Interface Valid Bits (W32p rev B + ?)
bit 0
M+34h (R/W): ACL Interrupt Mask Register
bit 0 Write Interrupt Enable. If set generates an interrupt when the queue
is next not-full (I.e. wake me when the transfer has completed).
Clear this bit to clear the resulting interrupt.
1 Read Interrupt Enable.
2 Write Fault Interrupt Enable.
M+35h (R/W): ACL Interrupt Status Register
bit 0 (R) If set a Write Interrupt is pending
1 If set a Read Interrupt is pending. Set the bit to clear the
Interrupt condition.
2 If set a Write Fault Interrupt is pending. Set the bit to clear the
Interrupt condition.
M+36h (R/W): ACL Accelerator Status Register
bit 0 (R) Write Status (WRST). If set the accelerators queue is full and
cannot accept further writes to the queued registers
1 (R) Read Status (RDST). If set the Accelerator is busy or the queue
is not empty
2 XY Status (XYST). If set the Accelerator is processing an X/Y block,
I.e. the internal XPOS/YPOS have not yet stabilised. When a
suspended operation is restored this bit must also be restored
3 (R) Screen-to Screen Status (SSO). Set if the current Accelerator
operation is screen-to-screen. This bit is only valid if bit 2 is
set
4 (R) Queue Modified Status (QMOD). If set a queued register has been
written since the last accelerator operation was started.
6 (W32p rev B +) Accelerator Pipeline not empty.
7 (W32p rev B +) Accelerator Data Ready Status. If set data waiting
for the host to read.
M+38h W(R/W): ACL X Position Register (W32p only)
bit 0-11 The accelerators current X position
Note: this register is at offset 94h in the W32 and W32i
M+3Ah W(R/W): ACL Y Position Register (W32p only)
bit 0-11 The accelerators current Y position
Note: this register is at offset 96h in the W32 and W32i
M+80h D(R/W): ACL Pattern Address Register
bit 0-21 The byte address in display memory of the Pattern Map
M+84h D(R/W): ACL Source Address Register
bit 0-21 The byte address in display memory of the Source Map
M+88h W(R/W): ACL Pattern Y Offset Register
bit 0-11 The number of bytes (-1) between lines in the pattern
M+8Ah W(R/W): ACL Source Y Offset Register
bit 0-11 The number of bytes (-1) between lines in the source
M+8Ch W(R/W): ACL Destination Y Offset Register
bit 0-11 The number of bytes (-1) between lines in the destination
M+8Eh (R/W): ACL Virtual Bus Size Register (W32,W32i only)
bit 0-1 Virtual Bus Size (VBS). When the host provides Source Map or Mix Map
data this is the number of bytes handled at a time. The number of
bytes transferred must be rounded up to an integral multiplum of
this number. 0: 1byte, 1: 2bytes, 2: 4bytes
M+8Eh (R/W): ACL Pixel Depth Register (W32p only)
bit 0-? Pixel depth. 0: 1 byte per pixel, 1: 2 bytes per pixel
M+8Fh (R/W): ACL X/Y Direction Register
bit 0 X Direction. If set the accelerator moves from high to low addresses
(right -> left), if clear from low to high (left -> right)
1 Y Direction. If set the accelerator moves from high to low addresses
(down -> up), if clear from low to high (up -> down)
0-2 (W32p) Axial Direction for linedraw
4 (W32p) Line Draw Algorithm.
5 (W32p) LETQ Load Error Term. If set the internal Bresenham Error
term is loaded from the ACL Error Term register (M+AAh) (used for
clipping), if clear it is automatically calculated from the ACL
Delta Major register (M+AEh) at the start of the line draw.
7 (W32p) Graphics Opcode. 0 for BitBLT, 1 for linedraw
M+90h (R/W): ACL Pattern Wrap Register
bit 0-2 Pattern X Wrap. The pattern Map will wrap back to the start when
this number of bytes have been processed.
2: 4bytes, 3: 8bytes, 4: 16bytes, 5: 32bytes, 6: 64bytes, 7:never
4-6 Pattern Y Wrap. The pattern Map will wrap back to the start when
this number of lines have been processed.
0: 1 line, 1: 2 lines, 2: 4 lines, 3: 8 lines, 7: never
M+92h (R/W): ACL Source Wrap Register
bit 0-2 Source X Wrap. The Source Map will wrap back to the start when
this number of bytes have been processed.
2: 4bytes, 3: 8bytes, 4: 16bytes, 5: 32bytes, 6: 64bytes, 7:never
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