clock.hier_info

电子课程设计数字钟的源代码

|clock
sound <= <GND>
q[0] <= DISPLAY:21.q[0]
q[1] <= DISPLAY:21.q[1]
q[2] <= DISPLAY:21.q[2]
q[3] <= DISPLAY:21.q[3]
q[4] <= DISPLAY:21.q[4]
q[5] <= DISPLAY:21.q[5]
q[6] <= DISPLAY:21.q[6]
CLK_50 => yiqianfp:inst1.CLK
reset => yiqianfp:inst1.rst
reset => yiqianfp:inst2.rst
reset => wushifp:inst3.rst
SEThour => 7400:inst9.3
SEThour => 7408:inst11.2
SETmin => 7400:inst6.3
SETmin => 7408:inst8.2
CLR => 6.IN0
CLR => MINUTE:18.en
CLR => HOUR:19.en
CLRM => MINSECONDB:49.clrm
STOP => MINSECONDB:49.stop
sel[0] <= weisel:inst.weisel[0]
sel[1] <= weisel:inst.weisel[1]
sel[2] <= weisel:inst.weisel[2]
sel[3] <= weisel:inst.weisel[3]
sel[4] <= weisel:inst.weisel[4]
sel[5] <= weisel:inst.weisel[5]
sel[6] <= weisel:inst.weisel[6]
sel[7] <= weisel:inst.weisel[7]


|clock|DISPLAY:21
d[0] => Mux~0.IN19
d[0] => Mux~1.IN19
d[0] => Mux~2.IN19
d[0] => Mux~3.IN19
d[0] => Mux~4.IN19
d[0] => Mux~5.IN19
d[0] => Mux~6.IN19
d[1] => Mux~0.IN18
d[1] => Mux~1.IN18
d[1] => Mux~2.IN18
d[1] => Mux~3.IN18
d[1] => Mux~4.IN18
d[1] => Mux~5.IN18
d[1] => Mux~6.IN18
d[2] => Mux~0.IN17
d[2] => Mux~1.IN17
d[2] => Mux~2.IN17
d[2] => Mux~3.IN17
d[2] => Mux~4.IN17
d[2] => Mux~5.IN17
d[2] => Mux~6.IN17
d[3] => Mux~0.IN16
d[3] => Mux~1.IN16
d[3] => Mux~2.IN16
d[3] => Mux~3.IN16
d[3] => Mux~4.IN16
d[3] => Mux~5.IN16
d[3] => Mux~6.IN16
q[0] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE


|clock|SELTIME:48
clk => count[1].CLK
clk => count[0].CLK
clk => count[2].CLK
secm1[0] => Mux~3.IN0
secm1[1] => Mux~2.IN0
secm1[2] => Mux~1.IN0
secm1[3] => Mux~0.IN0
secm0[0] => Mux~3.IN1
secm0[1] => Mux~2.IN1
secm0[2] => Mux~1.IN1
secm0[3] => Mux~0.IN1
sec1[0] => Mux~3.IN2
sec1[1] => Mux~2.IN2
sec1[2] => Mux~1.IN2
sec1[3] => Mux~0.IN2
sec0[0] => Mux~3.IN3
sec0[1] => Mux~2.IN3
sec0[2] => Mux~1.IN3
sec0[3] => Mux~0.IN3
min1[0] => Mux~3.IN4
min1[1] => Mux~2.IN4
min1[2] => Mux~1.IN4
min1[3] => Mux~0.IN4
min0[0] => Mux~3.IN5
min0[1] => Mux~2.IN5
min0[2] => Mux~1.IN5
min0[3] => Mux~0.IN5
h1[0] => Mux~3.IN6
h1[1] => Mux~2.IN6
h1[2] => Mux~1.IN6
h1[3] => Mux~0.IN6
h0[0] => Mux~3.IN7
h0[1] => Mux~2.IN7
h0[2] => Mux~1.IN7
h0[3] => Mux~0.IN7
daout[0] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
daout[1] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
daout[2] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
daout[3] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
sel[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
sel[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
sel[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE


|clock|yiqianfp:inst1
CLK => qn[8].CLK
CLK => qn[7].CLK
CLK => qn[6].CLK
CLK => qn[5].CLK
CLK => qn[4].CLK
CLK => qn[3].CLK
CLK => qn[2].CLK
CLK => qn[1].CLK
CLK => qn[0].CLK
CLK => qn[9].CLK
rst => qn[8].ACLR
rst => qn[7].ACLR
rst => qn[6].ACLR
rst => qn[5].ACLR
rst => qn[4].ACLR
rst => qn[3].ACLR
rst => qn[2].ACLR
rst => qn[1].ACLR
rst => qn[0].ACLR
rst => qn[9].ACLR
CNT <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|clock|HOUR:19
clk => cnt1[2].CLK
clk => cnt1[1].CLK
clk => cnt1[0].CLK
clk => cnt0[3].CLK
clk => cnt0[2].CLK
clk => cnt0[1].CLK
clk => cnt0[0].CLK
clk => cnt1[3].CLK
en => cnt1[2].ENA
en => cnt1[1].ENA
en => cnt1[0].ENA
en => cnt0[3].ENA
en => cnt0[2].ENA
en => cnt0[1].ENA
en => cnt0[0].ENA
en => cnt1[3].ENA
h1[0] <= cnt1[0].DB_MAX_OUTPUT_PORT_TYPE
h1[1] <= cnt1[1].DB_MAX_OUTPUT_PORT_TYPE
h1[2] <= cnt1[2].DB_MAX_OUTPUT_PORT_TYPE
h1[3] <= cnt1[3].DB_MAX_OUTPUT_PORT_TYPE
h0[0] <= cnt0[0].DB_MAX_OUTPUT_PORT_TYPE
h0[1] <= cnt0[1].DB_MAX_OUTPUT_PORT_TYPE
h0[2] <= cnt0[2].DB_MAX_OUTPUT_PORT_TYPE
h0[3] <= cnt0[3].DB_MAX_OUTPUT_PORT_TYPE


|clock|7432:inst10
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1


|clock|7400:inst9
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1


|clock|MINUTE:18
clk => cnt0[3].CLK
clk => cnt0[2].CLK
clk => cnt0[1].CLK
clk => cnt0[0].CLK
clk => cnt1[3].CLK
clk => cnt1[2].CLK
clk => cnt1[1].CLK
clk => cnt1[0].CLK
clk => co~reg0.CLK
en => cnt0[3].ENA
en => cnt0[2].ENA
en => cnt0[1].ENA
en => cnt0[0].ENA
en => co~reg0.ENA
min1[0] <= cnt1[0].DB_MAX_OUTPUT_PORT_TYPE
min1[1] <= cnt1[1].DB_MAX_OUTPUT_PORT_TYPE
min1[2] <= cnt1[2].DB_MAX_OUTPUT_PORT_TYPE
min1[3] <= cnt1[3].DB_MAX_OUTPUT_PORT_TYPE
min0[0] <= cnt0[0].DB_MAX_OUTPUT_PORT_TYPE
min0[1] <= cnt0[1].DB_MAX_OUTPUT_PORT_TYPE
min0[2] <= cnt0[2].DB_MAX_OUTPUT_PORT_TYPE
min0[3] <= cnt0[3].DB_MAX_OUTPUT_PORT_TYPE
co <= co~reg0.DB_MAX_OUTPUT_PORT_TYPE


|clock|7432:inst7
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1


|clock|7400:inst6
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1


|clock|SECOND:17
clk => cnt1[2].CLK
clk => cnt1[1].CLK
clk => cnt1[0].CLK
clk => cnt0[3].CLK
clk => cnt0[2].CLK
clk => cnt0[1].CLK
clk => cnt0[0].CLK
clk => co~reg0.CLK
clk => cnt1[3].CLK
clr => cnt1[2].ACLR
clr => cnt1[1].ACLR
clr => cnt1[0].ACLR
clr => cnt0[3].ACLR
clr => cnt0[2].ACLR
clr => cnt0[1].ACLR
clr => cnt0[0].ACLR
clr => cnt1[3].ACLR
clr => co~reg0.ENA
sec1[0] <= cnt1[0].DB_MAX_OUTPUT_PORT_TYPE
sec1[1] <= cnt1[1].DB_MAX_OUTPUT_PORT_TYPE
sec1[2] <= cnt1[2].DB_MAX_OUTPUT_PORT_TYPE
sec1[3] <= cnt1[3].DB_MAX_OUTPUT_PORT_TYPE
sec0[0] <= cnt0[0].DB_MAX_OUTPUT_PORT_TYPE
sec0[1] <= cnt0[1].DB_MAX_OUTPUT_PORT_TYPE
sec0[2] <= cnt0[2].DB_MAX_OUTPUT_PORT_TYPE
sec0[3] <= cnt0[3].DB_MAX_OUTPUT_PORT_TYPE
co <= co~reg0.DB_MAX_OUTPUT_PORT_TYPE


|clock|wushifp:inst3
CLK => qn[4].CLK
CLK => qn[3].CLK
CLK => qn[2].CLK
CLK => qn[1].CLK
CLK => qn[0].CLK
CLK => qn[5].CLK
rst => qn[4].ACLR
rst => qn[3].ACLR
rst => qn[2].ACLR
rst => qn[1].ACLR
rst => qn[0].ACLR
rst => qn[5].ACLR
CNT <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|clock|yiqianfp:inst2
CLK => qn[8].CLK
CLK => qn[7].CLK
CLK => qn[6].CLK
CLK => qn[5].CLK
CLK => qn[4].CLK
CLK => qn[3].CLK
CLK => qn[2].CLK
CLK => qn[1].CLK
CLK => qn[0].CLK
CLK => qn[9].CLK
rst => qn[8].ACLR
rst => qn[7].ACLR
rst => qn[6].ACLR
rst => qn[5].ACLR
rst => qn[4].ACLR
rst => qn[3].ACLR
rst => qn[2].ACLR
rst => qn[1].ACLR
rst => qn[0].ACLR
rst => qn[9].ACLR
CNT <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|clock|7408:inst8
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1


|clock|7408:inst11
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1


|clock|MINSECONDb:49
clk => cnt1[3].CLK
clk => cnt1[2].CLK
clk => cnt1[1].CLK
clk => cnt1[0].CLK
clk => cnt0[3].CLK
clk => cnt0[2].CLK
clk => cnt0[1].CLK
clk => cnt0[0].CLK
clk => co~reg0.CLK
clrm => cnt1[2].ACLR
clrm => cnt1[1].ACLR
clrm => cnt1[0].ACLR
clrm => cnt0[3].ACLR
clrm => cnt0[2].ACLR
clrm => cnt0[1].ACLR
clrm => cnt0[0].ACLR
clrm => cnt1[3].ACLR
clrm => co~reg0.ENA
stop => ~NO_FANOUT~
secm1[0] <= cnt1[0].DB_MAX_OUTPUT_PORT_TYPE
secm1[1] <= cnt1[1].DB_MAX_OUTPUT_PORT_TYPE
secm1[2] <= cnt1[2].DB_MAX_OUTPUT_PORT_TYPE
secm1[3] <= cnt1[3].DB_MAX_OUTPUT_PORT_TYPE
secm0[0] <= cnt0[0].DB_MAX_OUTPUT_PORT_TYPE
secm0[1] <= cnt0[1].DB_MAX_OUTPUT_PORT_TYPE
secm0[2] <= cnt0[2].DB_MAX_OUTPUT_PORT_TYPE
secm0[3] <= cnt0[3].DB_MAX_OUTPUT_PORT_TYPE
co <= co~reg0.DB_MAX_OUTPUT_PORT_TYPE


|clock|weisel:inst
sel[0] => Mux~0.IN10
sel[0] => Mux~1.IN10
sel[0] => Mux~2.IN10
sel[0] => Mux~3.IN10
sel[0] => Mux~4.IN10
sel[0] => Mux~5.IN10
sel[0] => Mux~6.IN10
sel[0] => Mux~7.IN10
sel[1] => Mux~0.IN9
sel[1] => Mux~1.IN9
sel[1] => Mux~2.IN9
sel[1] => Mux~3.IN9
sel[1] => Mux~4.IN9
sel[1] => Mux~5.IN9
sel[1] => Mux~6.IN9
sel[1] => Mux~7.IN9
sel[2] => Mux~0.IN8
sel[2] => Mux~1.IN8
sel[2] => Mux~2.IN8
sel[2] => Mux~3.IN8
sel[2] => Mux~4.IN8
sel[2] => Mux~5.IN8
sel[2] => Mux~6.IN8
sel[2] => Mux~7.IN8
weisel[0] <= Mux~7.DB_MAX_OUTPUT_PORT_TYPE
weisel[1] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
weisel[2] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
weisel[3] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
weisel[4] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
weisel[5] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
weisel[6] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
weisel[7] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE


|clock|ALERT:16
m1[0] => reduce_nor~0.IN2
m1[1] => reduce_nor~0.IN1
m1[2] => reduce_nor~0.IN3
m1[3] => reduce_nor~0.IN0
m0[0] => reduce_nor~1.IN2
m0[1] => reduce_nor~1.IN1
m0[2] => reduce_nor~1.IN0
m0[3] => reduce_nor~1.IN3
s1[0] => reduce_nor~2.IN2
s1[1] => reduce_nor~2.IN1
s1[2] => reduce_nor~2.IN3
s1[3] => reduce_nor~2.IN0
s0[0] => reduce_nor~3.IN2
s0[0] => reduce_nor~4.IN2
s0[0] => reduce_nor~5.IN2
s0[0] => reduce_nor~6.IN2
s0[0] => reduce_nor~7.IN2
s0[1] => reduce_nor~3.IN1
s0[1] => reduce_nor~5.IN1
s0[1] => reduce_nor~7.IN1
s0[1] => reduce_nor~4.IN1
s0[1] => reduce_nor~6.IN1
s0[2] => reduce_nor~3.IN0
s0[2] => reduce_nor~4.IN0
s0[2] => reduce_nor~7.IN0
s0[2] => reduce_nor~5.IN0
s0[2] => reduce_nor~6.IN0
s0[3] => reduce_nor~3.IN3
s0[3] => reduce_nor~4.IN3
s0[3] => reduce_nor~5.IN3
s0[3] => reduce_nor~6.IN3
s0[3] => reduce_nor~7.IN3
clk => qlk~reg0.CLK
clk => q500~reg0.CLK
q500 <= q500~reg0.DB_MAX_OUTPUT_PORT_TYPE
qlk <= qlk~reg0.DB_MAX_OUTPUT_PORT_TYPE