clock.map.qmsg

电子课程设计数字钟的源代码

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus50/libraries/others/maxplus2/7400.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/others/maxplus2/7400.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7400 " "Info: Found entity 1: 7400" {  } { { "7400.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7400.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7400 7400:inst9 " "Info: Elaborating entity \"7400\" for hierarchy \"7400:inst9\"" {  } { { "clock.bdf" "inst9" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 672 232 296 712 "inst9" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MINUTE MINUTE:18 " "Info: Elaborating entity \"MINUTE\" for hierarchy \"MINUTE:18\"" {  } { { "clock.bdf" "18" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 520 624 776 600 "18" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SECOND SECOND:17 " "Info: Elaborating entity \"SECOND\" for hierarchy \"SECOND:17\"" {  } { { "clock.bdf" "17" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 408 624 776 488 "17" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "wushifp wushifp:inst3 " "Info: Elaborating entity \"wushifp\" for hierarchy \"wushifp:inst3\"" {  } { { "clock.bdf" "inst3" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 248 192 288 344 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus50/libraries/others/maxplus2/7408.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/others/maxplus2/7408.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7408 " "Info: Found entity 1: 7408" {  } { { "7408.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7408.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7408 7408:inst8 " "Info: Elaborating entity \"7408\" for hierarchy \"7408:inst8\"" {  } { { "clock.bdf" "inst8" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 568 288 352 608 "inst8" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MINSECONDb MINSECONDb:49 " "Info: Elaborating entity \"MINSECONDb\" for hierarchy \"MINSECONDb:49\"" {  } { { "clock.bdf" "49" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 752 592 760 832 "49" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clk1 minsecondb.vhd(11) " "Info: (10035) Verilog HDL or VHDL information at minsecondb.vhd(11): object \"clk1\" declared but not used" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 11 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "weisel weisel:inst " "Info: Elaborating entity \"weisel\" for hierarchy \"weisel:inst\"" {  } { { "clock.bdf" "inst" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 504 1216 1368 600 "inst" "" } } } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "weisel.vhd(25) " "Info: VHDL Case Statement information at weisel.vhd(25): OTHERS choice is never selected" {  } { { "weisel.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/weisel.vhd" 25 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ALERT ALERT:16 " "Info: Elaborating entity \"ALERT\" for hierarchy \"ALERT:16\"" {  } { { "clock.bdf" "16" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 264 624 768 376 "16" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "MINSECONDb:49\|cnt1\[3\] " "Warning: No clock transition on register \"MINSECONDb:49\|cnt1\[3\]\" due to stuck clock or clock enable" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "MINSECONDb:49\|cnt1\[3\] clock GND " "Warning: Reduced register \"MINSECONDb:49\|cnt1\[3\]\" with stuck clock port to stuck value GND" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "MINSECONDb:49\|cnt1\[2\] " "Warning: No clock transition on register \"MINSECONDb:49\|cnt1\[2\]\" due to stuck clock or clock enable" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "MINSECONDb:49\|cnt1\[2\] clock GND " "Warning: Reduced register \"MINSECONDb:49\|cnt1\[2\]\" with stuck clock port to stuck value GND" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "MINSECONDb:49\|cnt1\[1\] " "Warning: No clock transition on register \"MINSECONDb:49\|cnt1\[1\]\" due to stuck clock or clock enable" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "MINSECONDb:49\|cnt1\[1\] clock GND " "Warning: Reduced register \"MINSECONDb:49\|cnt1\[1\]\" with stuck clock port to stuck value GND" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "MINSECONDb:49\|cnt1\[0\] " "Warning: No clock transition on register \"MINSECONDb:49\|cnt1\[0\]\" due to stuck clock or clock enable" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "MINSECONDb:49\|cnt1\[0\] clock GND " "Warning: Reduced register \"MINSECONDb:49\|cnt1\[0\]\" with stuck clock port to stuck value GND" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "MINSECONDb:49\|cnt0\[3\] " "Warning: No clock transition on register \"MINSECONDb:49\|cnt0\[3\]\" due to stuck clock or clock enable" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "MINSECONDb:49\|cnt0\[3\] clock GND " "Warning: Reduced register \"MINSECONDb:49\|cnt0\[3\]\" with stuck clock port to stuck value GND" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "MINSECONDb:49\|cnt0\[2\] " "Warning: No clock transition on register \"MINSECONDb:49\|cnt0\[2\]\" due to stuck clock or clock enable" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "MINSECONDb:49\|cnt0\[2\] clock GND " "Warning: Reduced register \"MINSECONDb:49\|cnt0\[2\]\" with stuck clock port to stuck value GND" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "MINSECONDb:49\|cnt0\[1\] " "Warning: No clock transition on register \"MINSECONDb:49\|cnt0\[1\]\" due to stuck clock or clock enable" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "MINSECONDb:49\|cnt0\[1\] clock GND " "Warning: Reduced register \"MINSECONDb:49\|cnt0\[1\]\" with stuck clock port to stuck value GND" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "MINSECONDb:49\|cnt0\[0\] " "Warning: No clock transition on register \"MINSECONDb:49\|cnt0\[0\]\" due to stuck clock or clock enable" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "MINSECONDb:49\|cnt0\[0\] clock GND " "Warning: Reduced register \"MINSECONDb:49\|cnt0\[0\]\" with stuck clock port to stuck value GND" {  } { { "minsecondb.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minsecondb.vhd" 15 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SECOND:17\|cnt1\[3\] data_in GND " "Warning: Reduced register \"SECOND:17\|cnt1\[3\]\" with stuck data_in port to stuck value GND" {  } { { "second.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/second.vhd" 13 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "MINUTE:18\|cnt1\[3\] data_in GND " "Warning: Reduced register \"MINUTE:18\|cnt1\[3\]\" with stuck data_in port to stuck value GND" {  } { { "minute.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/minute.vhd" 13 -1 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "sound GND " "Warning: Pin \"sound\" stuck at GND" {  } { { "clock.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 328 1224 1400 344 "sound" "" } } } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "2 " "Warning: Design contains 2 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "CLRM " "Warning: No output dependent on input pin \"CLRM\"" {  } { { "clock.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 784 152 320 800 "CLRM" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "STOP " "Warning: No output dependent on input pin \"STOP\"" {  } { { "clock.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 816 152 320 832 "STOP" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "142 " "Info: Implemented 142 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "119 " "Info: Implemented 119 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 35 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 22 17:41:21 2008 " "Info: Processing ended: Tue Jan 22 17:41:21 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Info: Elapsed time: 00:00:21" {  } {  } 0}  } {  } 0}