clock.tan.qmsg

电子课程设计数字钟的源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SEThour register HOUR:19\|cnt0\[1\] register HOUR:19\|cnt1\[1\] 197.94 MHz 5.052 ns Internal " "Info: Clock \"SEThour\" has Internal fmax of 197.94 MHz between source register \"HOUR:19\|cnt0\[1\]\" and destination register \"HOUR:19\|cnt1\[1\]\" (period= 5.052 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.791 ns + Longest register register " "Info: + Longest register to register delay is 4.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns HOUR:19\|cnt0\[1\] 1 REG LC_X26_Y14_N5 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y14_N5; Fanout = 7; REG Node = 'HOUR:19\|cnt0\[1\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "" { HOUR:19|cnt0[1] } "NODE_NAME" } "" } } { "hour.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/hour.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.166 ns) + CELL(0.590 ns) 1.756 ns HOUR:19\|LessThan~45 2 COMB LC_X27_Y14_N5 4 " "Info: 2: + IC(1.166 ns) + CELL(0.590 ns) = 1.756 ns; Loc. = LC_X27_Y14_N5; Fanout = 4; COMB Node = 'HOUR:19\|LessThan~45'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "1.756 ns" { HOUR:19|cnt0[1] HOUR:19|LessThan~45 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.418 ns) + CELL(0.432 ns) 2.606 ns HOUR:19\|add~175COUT1_195 3 COMB LC_X27_Y14_N0 2 " "Info: 3: + IC(0.418 ns) + CELL(0.432 ns) = 2.606 ns; Loc. = LC_X27_Y14_N0; Fanout = 2; COMB Node = 'HOUR:19\|add~175COUT1_195'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "0.850 ns" { HOUR:19|LessThan~45 HOUR:19|add~175COUT1_195 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 3.214 ns HOUR:19\|add~178 4 COMB LC_X27_Y14_N1 1 " "Info: 4: + IC(0.000 ns) + CELL(0.608 ns) = 3.214 ns; Loc. = LC_X27_Y14_N1; Fanout = 1; COMB Node = 'HOUR:19\|add~178'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "0.608 ns" { HOUR:19|add~175COUT1_195 HOUR:19|add~178 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.099 ns) + CELL(0.478 ns) 4.791 ns HOUR:19\|cnt1\[1\] 5 REG LC_X26_Y14_N7 5 " "Info: 5: + IC(1.099 ns) + CELL(0.478 ns) = 4.791 ns; Loc. = LC_X26_Y14_N7; Fanout = 5; REG Node = 'HOUR:19\|cnt1\[1\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "1.577 ns" { HOUR:19|add~178 HOUR:19|cnt1[1] } "NODE_NAME" } "" } } { "hour.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/hour.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 44.00 % " "Info: Total cell delay = 2.108 ns ( 44.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.683 ns 56.00 % " "Info: Total interconnect delay = 2.683 ns ( 56.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "4.791 ns" { HOUR:19|cnt0[1] HOUR:19|LessThan~45 HOUR:19|add~175COUT1_195 HOUR:19|add~178 HOUR:19|cnt1[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.791 ns" { HOUR:19|cnt0[1] HOUR:19|LessThan~45 HOUR:19|add~175COUT1_195 HOUR:19|add~178 HOUR:19|cnt1[1] } { 0.000ns 1.166ns 0.418ns 0.000ns 1.099ns } { 0.000ns 0.590ns 0.432ns 0.608ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SEThour destination 8.543 ns + Shortest register " "Info: + Shortest clock path from clock \"SEThour\" to destination register is 8.543 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SEThour 1 CLK PIN_164 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_164; Fanout = 1; CLK Node = 'SEThour'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "" { SEThour } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 712 -120 48 728 "SEThour" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.904 ns) + CELL(0.442 ns) 3.815 ns 7432:inst10\|4 2 COMB LC_X27_Y13_N7 8 " "Info: 2: + IC(1.904 ns) + CELL(0.442 ns) = 3.815 ns; Loc. = LC_X27_Y13_N7; Fanout = 8; COMB Node = '7432:inst10\|4'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "2.346 ns" { SEThour 7432:inst10|4 } "NODE_NAME" } "" } } { "7432.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7432.bdf" { { 160 296 360 200 "4" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.017 ns) + CELL(0.711 ns) 8.543 ns HOUR:19\|cnt1\[1\] 3 REG LC_X26_Y14_N7 5 " "Info: 3: + IC(4.017 ns) + CELL(0.711 ns) = 8.543 ns; Loc. = LC_X26_Y14_N7; Fanout = 5; REG Node = 'HOUR:19\|cnt1\[1\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "4.728 ns" { 7432:inst10|4 HOUR:19|cnt1[1] } "NODE_NAME" } "" } } { "hour.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/hour.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns 30.69 % " "Info: Total cell delay = 2.622 ns ( 30.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.921 ns 69.31 % " "Info: Total interconnect delay = 5.921 ns ( 69.31 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "8.543 ns" { SEThour 7432:inst10|4 HOUR:19|cnt1[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.543 ns" { SEThour SEThour~out0 7432:inst10|4 HOUR:19|cnt1[1] } { 0.000ns 0.000ns 1.904ns 4.017ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SEThour source 8.543 ns - Longest register " "Info: - Longest clock path from clock \"SEThour\" to source register is 8.543 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SEThour 1 CLK PIN_164 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_164; Fanout = 1; CLK Node = 'SEThour'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "" { SEThour } "NODE_NAME" } "" } } { "clock.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 712 -120 48 728 "SEThour" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.904 ns) + CELL(0.442 ns) 3.815 ns 7432:inst10\|4 2 COMB LC_X27_Y13_N7 8 " "Info: 2: + IC(1.904 ns) + CELL(0.442 ns) = 3.815 ns; Loc. = LC_X27_Y13_N7; Fanout = 8; COMB Node = '7432:inst10\|4'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "2.346 ns" { SEThour 7432:inst10|4 } "NODE_NAME" } "" } } { "7432.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7432.bdf" { { 160 296 360 200 "4" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.017 ns) + CELL(0.711 ns) 8.543 ns HOUR:19\|cnt0\[1\] 3 REG LC_X26_Y14_N5 7 " "Info: 3: + IC(4.017 ns) + CELL(0.711 ns) = 8.543 ns; Loc. = LC_X26_Y14_N5; Fanout = 7; REG Node = 'HOUR:19\|cnt0\[1\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "4.728 ns" { 7432:inst10|4 HOUR:19|cnt0[1] } "NODE_NAME" } "" } } { "hour.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/hour.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns 30.69 % " "Info: Total cell delay = 2.622 ns ( 30.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.921 ns 69.31 % " "Info: Total interconnect delay = 5.921 ns ( 69.31 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "8.543 ns" { SEThour 7432:inst10|4 HOUR:19|cnt0[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.543 ns" { SEThour SEThour~out0 7432:inst10|4 HOUR:19|cnt0[1] } { 0.000ns 0.000ns 1.904ns 4.017ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } }  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "8.543 ns" { SEThour 7432:inst10|4 HOUR:19|cnt1[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.543 ns" { SEThour SEThour~out0 7432:inst10|4 HOUR:19|cnt1[1] } { 0.000ns 0.000ns 1.904ns 4.017ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } } { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "8.543 ns" { SEThour 7432:inst10|4 HOUR:19|cnt0[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.543 ns" { SEThour SEThour~out0 7432:inst10|4 HOUR:19|cnt0[1] } { 0.000ns 0.000ns 1.904ns 4.017ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output