clock.fit.qmsg

电子课程设计数字钟的源代码

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "3 unused 3.30 2 1 0 " "Info: Number of I/O pins in group: 3 (unused VREF, 3.30 VCCIO, 2 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 4 40 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used --  40 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.30V 15 33 " "Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 15 total pin(s) used --  33 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 3 42 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  42 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.581 ns register register " "Info: Estimated most critical path is register to register delay of 3.581 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns HOUR:19\|cnt0\[0\] 1 REG LAB_X26_Y14 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X26_Y14; Fanout = 7; REG Node = 'HOUR:19\|cnt0\[0\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "" { HOUR:19|cnt0[0] } "NODE_NAME" } "" } } { "hour.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/hour.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.590 ns) 0.966 ns HOUR:19\|LessThan~45 2 COMB LAB_X27_Y14 4 " "Info: 2: + IC(0.376 ns) + CELL(0.590 ns) = 0.966 ns; Loc. = LAB_X27_Y14; Fanout = 4; COMB Node = 'HOUR:19\|LessThan~45'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "0.966 ns" { HOUR:19|cnt0[0] HOUR:19|LessThan~45 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.575 ns) 1.935 ns HOUR:19\|add~175COUT1_195 3 COMB LAB_X27_Y14 2 " "Info: 3: + IC(0.394 ns) + CELL(0.575 ns) = 1.935 ns; Loc. = LAB_X27_Y14; Fanout = 2; COMB Node = 'HOUR:19\|add~175COUT1_195'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "0.969 ns" { HOUR:19|LessThan~45 HOUR:19|add~175COUT1_195 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.543 ns HOUR:19\|add~178 4 COMB LAB_X27_Y14 1 " "Info: 4: + IC(0.000 ns) + CELL(0.608 ns) = 2.543 ns; Loc. = LAB_X27_Y14; Fanout = 1; COMB Node = 'HOUR:19\|add~178'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "0.608 ns" { HOUR:19|add~175COUT1_195 HOUR:19|add~178 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.738 ns) 3.581 ns HOUR:19\|cnt1\[1\] 5 REG LAB_X26_Y14 5 " "Info: 5: + IC(0.300 ns) + CELL(0.738 ns) = 3.581 ns; Loc. = LAB_X26_Y14; Fanout = 5; REG Node = 'HOUR:19\|cnt1\[1\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "1.038 ns" { HOUR:19|add~178 HOUR:19|cnt1[1] } "NODE_NAME" } "" } } { "hour.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/hour.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.511 ns 70.12 % " "Info: Total cell delay = 2.511 ns ( 70.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.070 ns 29.88 % " "Info: Total interconnect delay = 1.070 ns ( 29.88 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "3.581 ns" { HOUR:19|cnt0[0] HOUR:19|LessThan~45 HOUR:19|add~175COUT1_195 HOUR:19|add~178 HOUR:19|cnt1[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "sound GND " "Info: Pin sound has GND driving its datain port" {  } { { "clock.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.bdf" { { 328 1224 1400 344 "sound" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sound" } } } } { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" "" { Report "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/db/clock.quartus_db" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/" "" "" { sound } "NODE_NAME" } "" } } { "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.fld" "" { Floorplan "C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.fld" "" "" { sound } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 22 17:41:39 2008 " "Info: Processing ended: Tue Jan 22 17:41:39 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" {  } {  } 0}  } {  } 0}