clock.map.rpt

电子课程设计数字钟的源代码

; |clock                     ; 119 (0)     ; 53           ; 0           ; 23   ; 0            ; 66 (0)       ; 6 (0)             ; 47 (0)           ; 30 (0)          ; |clock                ;
;    |7432:inst10|           ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |clock|7432:inst10    ;
;    |7432:inst7|            ; 1 (1)       ; 0            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |clock|7432:inst7     ;
;    |DISPLAY:21|            ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |clock|DISPLAY:21     ;
;    |HOUR:19|               ; 17 (17)     ; 8            ; 0           ; 0    ; 0            ; 9 (9)        ; 3 (3)             ; 5 (5)            ; 4 (4)           ; |clock|HOUR:19        ;
;    |MINUTE:18|             ; 15 (15)     ; 8            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 8 (8)            ; 0 (0)           ; |clock|MINUTE:18      ;
;    |SECOND:17|             ; 12 (12)     ; 8            ; 0           ; 0    ; 0            ; 4 (4)        ; 0 (0)             ; 8 (8)            ; 0 (0)           ; |clock|SECOND:17      ;
;    |SELTIME:48|            ; 18 (18)     ; 3            ; 0           ; 0    ; 0            ; 15 (15)      ; 3 (3)             ; 0 (0)            ; 0 (0)           ; |clock|SELTIME:48     ;
;    |weisel:inst|           ; 9 (9)       ; 0            ; 0           ; 0    ; 0            ; 9 (9)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |clock|weisel:inst    ;
;    |wushifp:inst3|         ; 9 (9)       ; 6            ; 0           ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 6 (6)            ; 6 (6)           ; |clock|wushifp:inst3  ;
;    |yiqianfp:inst1|        ; 15 (15)     ; 10           ; 0           ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 10 (10)          ; 10 (10)         ; |clock|yiqianfp:inst1 ;
;    |yiqianfp:inst2|        ; 15 (15)     ; 10           ; 0           ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 10 (10)          ; 10 (10)         ; |clock|yiqianfp:inst2 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 53    ;
; Number of registers using Synchronous Clear  ; 26    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 33    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 19    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |clock|SECOND:17|cnt0[3]   ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |clock|MINUTE:18|cnt0[1]   ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |clock|MINUTE:18|cnt0[0]   ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |clock|HOUR:19|cnt0[0]     ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |clock|SECOND:17|cnt1[2]   ;
; 8:1                ; 4 bits    ; 20 LEs        ; 16 LEs               ; 4 LEs                  ; No         ; |clock|SELTIME:48|daout[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/Administrator/桌面/复件 复件 clock/clock.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Jan 22 17:41:01 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 2 design units, including 1 entities, in source file alert.vhd
    Info: Found design unit 1: ALERT-sss_arc
    Info: Found entity 1: ALERT
Info: Found 2 design units, including 1 entities, in source file display.vhd
    Info: Found design unit 1: DISPLAY-disp_are
    Info: Found entity 1: DISPLAY
Info: Found 2 design units, including 1 entities, in source file hour.vhd
    Info: Found design unit 1: HOUR-hour_arc
    Info: Found entity 1: HOUR
Info: Found 2 design units, including 1 entities, in source file minsecond.vhd
    Info: Found design unit 1: MINSECOND_a-SEC
    Info: Found entity 1: MINSECOND_a
Info: Found 2 design units, including 1 entities, in source file minsecondb.vhd
    Info: Found design unit 1: MINSECONDb-SEC
    Info: Found entity 1: MINSECONDb
Info: Found 2 design units, including 1 entities, in source file minute.vhd
    Info: Found design unit 1: MINUTE-MIN
    Info: Found entity 1: MINUTE
Info: Found 2 design units, including 1 entities, in source file second.vhd
    Info: Found design unit 1: SECOND-SEC
    Info: Found entity 1: SECOND
Info: Found 2 design units, including 1 entities, in source file seltime.vhd
    Info: Found design unit 1: SELTIME-fun
    Info: Found entity 1: SELTIME
Info: Found 1 design units, including 1 entities, in source file clock.bdf
    Info: Found entity 1: clock
Info: Found 2 design units, including 1 entities, in source file yiqianfp.vhd
    Info: Found design unit 1: yiqianfp-fenpin
    Info: Found entity 1: yiqianfp
Info: Found 2 design units, including 1 entities, in source file wushifp.vhd
    Info: Found design unit 1: wushifp-fenpin
    Info: Found entity 1: wushifp
Info: Found 2 design units, including 1 entities, in source file weisel.vhd
    Info: Found design unit 1: weisel-module
    Info: Found entity 1: weisel
Info: Elaborating entity "clock" for the top level hierarchy
Warning: Pin "sound" is missing source
Warning: Port "clk" of type MINSECONDB and instance "49" is missing source signal
Warning: Port "clk" of type ALERT and instance "16" is missing source signal
Info: Elaborating entity "DISPLAY" for hierarchy "DISPLAY:21"
Info: Elaborating entity "SELTIME" for hierarchy "SELTIME:48"
Warning: VHDL Process Statement warning at seltime.vhd(25): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at seltime.vhd(26): signal "secm0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at seltime.vhd(27): signal "secm1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at seltime.vhd(28): signal "sec0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at seltime.vhd(29): signal "sec1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at seltime.vhd(30): signal "min0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at seltime.vhd(31): signal "min1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at seltime.vhd(32): signal "h0" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at seltime.vhd(33): signal "h1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: VHDL Case Statement information at seltime.vhd(34): OTHERS choice is never selected
Info: Elaborating entity "yiqianfp" for hierarchy "yiqianfp:inst1"
Info: Elaborating entity "HOUR" for hierarchy "HOUR:19"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/others/maxplus2/7432.bdf
    Info: Found entity 1: 7432
Info: Elaborating entity "7432" for hierarchy "7432:inst10"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/others/maxplus2/7400.bdf
    Info: Found entity 1: 7400
Info: Elaborating entity "7400" for hierarchy "7400:inst9"
Info: Elaborating entity "MINUTE" for hierarchy "MINUTE:18"
Info: Elaborating entity "SECOND" for hierarchy "SECOND:17"
Info: Elaborating entity "wushifp" for hierarchy "wushifp:inst3"
Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/others/maxplus2/7408.bdf
    Info: Found entity 1: 7408
Info: Elaborating entity "7408" for hierarchy "7408:inst8"
Info: Elaborating entity "MINSECONDb" for hierarchy "MINSECONDb:49"
Info: (10035) Verilog HDL or VHDL information at minsecondb.vhd(11): object "clk1" declared but not used
Info: Elaborating entity "weisel" for hierarchy "weisel:inst"
Info: VHDL Case Statement information at weisel.vhd(25): OTHERS choice is never selected
Info: Elaborating entity "ALERT" for hierarchy "ALERT:16"
Warning: No clock transition on register "MINSECONDb:49|cnt1[3]" due to stuck clock or clock enable
Warning: Reduced register "MINSECONDb:49|cnt1[3]" with stuck clock port to stuck value GND
Warning: No clock transition on register "MINSECONDb:49|cnt1[2]" due to stuck clock or clock enable
Warning: Reduced register "MINSECONDb:49|cnt1[2]" with stuck clock port to stuck value GND
Warning: No clock transition on register "MINSECONDb:49|cnt1[1]" due to stuck clock or clock enable
Warning: Reduced register "MINSECONDb:49|cnt1[1]" with stuck clock port to stuck value GND
Warning: No clock transition on register "MINSECONDb:49|cnt1[0]" due to stuck clock or clock enable
Warning: Reduced register "MINSECONDb:49|cnt1[0]" with stuck clock port to stuck value GND
Warning: No clock transition on register "MINSECONDb:49|cnt0[3]" due to stuck clock or clock enable
Warning: Reduced register "MINSECONDb:49|cnt0[3]" with stuck clock port to stuck value GND
Warning: No clock transition on register "MINSECONDb:49|cnt0[2]" due to stuck clock or clock enable
Warning: Reduced register "MINSECONDb:49|cnt0[2]" with stuck clock port to stuck value GND
Warning: No clock transition on register "MINSECONDb:49|cnt0[1]" due to stuck clock or clock enable
Warning: Reduced register "MINSECONDb:49|cnt0[1]" with stuck clock port to stuck value GND
Warning: No clock transition on register "MINSECONDb:49|cnt0[0]" due to stuck clock or clock enable
Warning: Reduced register "MINSECONDb:49|cnt0[0]" with stuck clock port to stuck value GND
Warning: Reduced register "SECOND:17|cnt1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "MINUTE:18|cnt1[3]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "sound" stuck at GND
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "CLRM"
    Warning: No output dependent on input pin "STOP"
Info: Implemented 142 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 16 output pins
    Info: Implemented 119 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings
    Info: Processing ended: Tue Jan 22 17:41:21 2008
    Info: Elapsed time: 00:00:21