shijian.vhd

VHDL的数字电子钟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity shijian is
port(clk: in std_logic;
     clk_tiao: in std_logic;
     kz1: in std_logic;
     kz2: in std_logic;
     day: out std_logic;
     day_y: out std_logic;
     shi_high:  out std_logic_vector(3 downto 0);
     shi_low:   out std_logic_vector(3 downto 0);
     fen_high:  out std_logic_vector(3 downto 0);
     fen_low:   out std_logic_vector(3 downto 0);
     miao_high: out std_logic_vector(3 downto 0);
     miao_low:  out std_logic_vector(3 downto 0));
end shijian;
architecture a of shijian is
component counter24 
port(clk: in std_logic;
      en: in std_logic;
      co: out std_logic;
      high: out std_logic_vector(3 downto 0);
      low:  out std_logic_vector(3 downto 0));
end component;
component counter60  
port(clk: in std_logic;
      en: in std_logic;
      co :out std_logic;
      high: out std_logic_vector(3 downto 0);
      low:  out std_logic_vector(3 downto 0));
end component;
component xuanze 
port(xinhao1: in std_logic;
     xinhao2: in std_logic;
     kongzhi: in std_logic;
       input: in std_logic;     
     xinhao:  out std_logic;
     output:  out std_logic);
end component;
signal x1,x2,y1,c1,c2,temp:std_logic;
begin
 temp<='0';
 u1:counter60 port map(clk,temp,x1,miao_high,miao_low);
 u2:counter60 port map(c1,temp,x2,fen_high,fen_low);
 u3:counter24 port map(c2,temp,day,shi_high,shi_low);
 u4:xuanze port map(x1,clk_tiao,kz1,temp,c1,y1);
 u5:xuanze port map(x2,clk_tiao,kz2,y1,c2,day_y);
 end a;