sheding.vhd

VHDL的数字电子钟程序

---------------------------sheding--------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity sheding is 
port(clk_tiao: in std_logic;
      tx: in std_logic;
      en: in std_logic;
      h_high: out std_logic_vector(3 downto 0);
      h_low:  out std_logic_vector(3 downto 0);
      m_high: out std_logic_vector(3 downto 0);
      m_low:  out std_logic_vector(3 downto 0);
      s_high: out std_logic_vector(3 downto 0);
      s_low:  out std_logic_vector(3 downto 0));
end sheding;
architecture a of sheding is
signal high1,low1,high2,low2:std_logic_vector(3 downto 0);
signal clk_tiao1: std_logic;
begin
p1:process(clk_tiao,en)
   begin
    s_high<="0000"; 
    s_low<="0000";
    if(en='0')then clk_tiao1<='0';
    else clk_tiao1<=clk_tiao;
    end if;
   end process; 
p2:process(clk_tiao1,tx)
  begin
    if(tx='0')then null;
    elsif(clk_tiao1'event and clk_tiao1='1')then 
      if(high1="0010" and low1="0011")then high1<="0000";
                                           low1<="0000";
        elsif(low1="1001")then  low1<="0000";
                               high1<=high1+1;
          else low1<=low1+1;
       end if;
    end if;
  h_high<=high1;h_low<=low1;
  end process;
p3:process(clk_tiao1,tx)
  begin
    if(tx='1')then null;
    elsif(clk_tiao1'event and clk_tiao1='1')then 
      if(high2="0101" and low2="1001")then high2<="0000";
                                           low2<="0000";
        elsif(low2="1001")then  low2<="0000";
                               high2<=high2+1;
          else low2<=low2+1;
       end if;
    end if;
   m_high<=high2;m_low<=low2;
  end process;   
end a;