xuanze.vhd

VHDL的数字电子钟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity xuanze is
port(xinhao1: in std_logic;
     xinhao2: in std_logic;
     kongzhi: in std_logic;
       input: in std_logic;     
     xinhao:  out std_logic;
     output:  out std_logic);
end xuanze;
architecture a of xuanze is
begin
process(kongzhi,input)
begin 
  if(input='1') then xinhao<='0';
  elsif(kongzhi='1') then xinhao<=xinhao2;
                     output<='1'; 
  else xinhao<=xinhao1; 
       output<='0';
  end if;
end process;
end a;