clock_2.vhd

VHDL的数字电子钟程序

      en: in std_logic;
      co :out std_logic;
      high: out std_logic_vector(3 downto 0);
      low:  out std_logic_vector(3 downto 0));
end counter60;
architecture a of counter60 is
signal high1,low1:std_logic_vector(3 downto 0);
begin
 process(clk,en)
  begin 
    if(en='1')then low1<="0000";
                   high1<="0000";
     elsif(clk'event and clk='1')then 
      if(high1="0101" and low1="1001")then high1<="0000";
                                           low1<="0000";
                                           co<='1';
        elsif(low1="1001")then  low1<="0000";high1<=high1+1;
          else low1<=low1+1;co<='0';
       end if;
    end if;
    high<=high1; low<=low1;
  end process;   
end a;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity xuanze is
port(xinhao1: in std_logic;
     xinhao2: in std_logic;
     kongzhi: in std_logic;
       input: in std_logic;     
     xinhao:  out std_logic;
     output:  out std_logic);
end xuanze;
architecture a of xuanze is
begin
process(kongzhi,input)
begin 
  if(input='1') then xinhao<='0';
  elsif(kongzhi='1') then xinhao<=xinhao2;
                     output<='1'; 
  else xinhao<=xinhao1; 
       output<='0';
  end if;
end process;
end a;  

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity shijian is
port(clk: in std_logic;
     clk_tiao: in std_logic;
     kz1: in std_logic;
     kz2: in std_logic;
     day: out std_logic;
     day_y: out std_logic;
     shi_high:  out std_logic_vector(3 downto 0);
     shi_low:   out std_logic_vector(3 downto 0);
     fen_high:  out std_logic_vector(3 downto 0);
     fen_low:   out std_logic_vector(3 downto 0);
     miao_high: out std_logic_vector(3 downto 0);
     miao_low:  out std_logic_vector(3 downto 0));
end shijian;
architecture a of shijian is
component counter24 
port(clk: in std_logic;
      en: in std_logic;
      co: out std_logic;
      high: out std_logic_vector(3 downto 0);
      low:  out std_logic_vector(3 downto 0));
end component;
component counter60  
port(clk: in std_logic;
      en: in std_logic;
      co :out std_logic;
      high: out std_logic_vector(3 downto 0);
      low:  out std_logic_vector(3 downto 0));
end component;
component xuanze 
port(xinhao1: in std_logic;
     xinhao2: in std_logic;
     kongzhi: in std_logic;
       input: in std_logic;     
     xinhao:  out std_logic;
     output:  out std_logic);
end component;
signal x1,x2,y1,c1,c2,temp:std_logic;
begin
 temp<='0';
 u1:counter60 port map(clk,temp,x1,miao_high,miao_low);
 u2:counter60 port map(c1,temp,x2,fen_high,fen_low);
 u3:counter24 port map(c2,temp,day,shi_high,shi_low);
 u4:xuanze port map(x1,clk_tiao,kz1,temp,c1,y1);
 u5:xuanze port map(x2,clk_tiao,kz2,y1,c2,day_y);
 end a;
-------------------------xsxuanze---------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;

entity xsxuanze is
port(h_high : in std_logic_vector(3 downto 0);
     h_low : in std_logic_vector(3 downto 0);
     m_high : in std_logic_vector(3 downto 0);
     m_low : in std_logic_vector(3 downto 0);
     s_high: in std_logic_vector(3 downto 0);
     s_low: in std_logic_vector(3 downto 0);
     sdh_high : in std_logic_vector(3 downto 0);
     sdh_low : in std_logic_vector(3 downto 0);
     sdm_high : in std_logic_vector(3 downto 0);
     sdm_low : in std_logic_vector(3 downto 0);
     sds_high: in std_logic_vector(3 downto 0);
     sds_low: in std_logic_vector(3 downto 0);
     en : in std_logic;
     clk: in std_logic;
     x1 : out std_logic_vector(3 downto 0);
     x2 : out std_logic_vector(3 downto 0);
     y1 : out std_logic_vector(3 downto 0);
     y2 : out std_logic_vector(3 downto 0);
     z1:  out std_logic_vector(3 downto 0);
     z2:  out std_logic_vector(3 downto 0));
end xsxuanze;
architecture a of xsxuanze is
begin
process(clk)
begin
if(en='0')then
  x1<=h_high;
  x2<=h_low;
  y1<=m_high;
  y2<=m_low;
  z1<=s_high;
  z2<=s_low;
else  x1<=sdh_high;
      x2<=sdh_low;
      y1<=sdm_high;
      y2<=sdm_low;
      z1<=sds_high;
      z2<=sds_low;
end if;
end process;
end a;
----------------------zhu cheng xu--------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity zhongbiao is
port(clk: in std_logic;
     clk_tiao1: in std_logic;
     clk_tiao2: in std_logic;
     a: in std_logic;
     b: in std_logic;
     c: in std_logic;
     d: in std_logic;
     kz: out std_logic;
     shi_h: out std_logic_vector(3 downto 0);
     shi_l: out std_logic_vector(3 downto 0);
     fen_h: out std_logic_vector(3 downto 0);
     fen_l: out std_logic_vector(3 downto 0);
     miao_h:out std_logic_vector(3 downto 0);
     miao_l:out std_logic_vector(3 downto 0));
end zhongbiao;
architecture a of zhongbiao is
component bszz 
port(clk1000:in std_logic;
     clk500:in std_logic;
     en: in std_logic;
     s_h: in std_logic_vector(3 downto 0);
     s_l: in std_logic_vector(3 downto 0);
     f_h: in std_logic_vector(3 downto 0);
     f_l: in std_logic_vector(3 downto 0);
     m_h: in std_logic_vector(3 downto 0);
     m_l: in std_logic_vector(3 downto 0);
     p_h: in std_logic_vector(3 downto 0);
     h1 : in std_logic_vector(3 downto 0);
     h2 : in std_logic_vector(3 downto 0);
     f1 : in std_logic_vector(3 downto 0);
     f2 : in std_logic_vector(3 downto 0);
     kz: out std_logic);
end component;

component fenpinqi 
port(clk:in std_logic;
     clk_500hz:out std_logic;
     clk_1hz:out std_logic;
     pm_h: out std_logic_vector(3 downto 0);
     pm_l:  out std_logic_vector(3 downto 0));
end component;

component kzyima 
port(a: in std_logic;
     b: in std_logic;
     c: in std_logic;
     mx: out std_logic;
     en: out std_logic;
     tx: out std_logic;
     k1: out std_logic;
     k2: out std_logic);
end component;
component sheding 
port(clk_tiao: in std_logic;
      tx: in std_logic;
      en: in std_logic;
      h_high: out std_logic_vector(3 downto 0);
      h_low:  out std_logic_vector(3 downto 0);
      m_high: out std_logic_vector(3 downto 0);
      m_low:  out std_logic_vector(3 downto 0);
      s_high: out std_logic_vector(3 downto 0);
      s_low:  out std_logic_vector(3 downto 0));
end component;
component shijian
port(clk: in std_logic;
     clk_tiao: in std_logic;
     kz1: in std_logic;
     kz2: in std_logic;
     day: out std_logic;
     day_y: out std_logic;
     shi_high:  out std_logic_vector(3 downto 0);
     shi_low:   out std_logic_vector(3 downto 0);
     fen_high:  out std_logic_vector(3 downto 0);
     fen_low:   out std_logic_vector(3 downto 0);
     miao_high: out std_logic_vector(3 downto 0);
     miao_low:  out std_logic_vector(3 downto 0));
end component;
component xsxuanze 
port(h_high : in std_logic_vector(3 downto 0);
     h_low : in std_logic_vector(3 downto 0);
     m_high : in std_logic_vector(3 downto 0);
     m_low : in std_logic_vector(3 downto 0);
     s_high: in std_logic_vector(3 downto 0);
     s_low: in std_logic_vector(3 downto 0);
     sdh_high : in std_logic_vector(3 downto 0);
     sdh_low : in std_logic_vector(3 downto 0);
     sdm_high : in std_logic_vector(3 downto 0);
     sdm_low : in std_logic_vector(3 downto 0);
     sds_high: in std_logic_vector(3 downto 0);
     sds_low: in std_logic_vector(3 downto 0);
     en : in std_logic;
     clk: in std_logic;
     x1 : out std_logic_vector(3 downto 0);
     x2 : out std_logic_vector(3 downto 0);
     y1 : out std_logic_vector(3 downto 0);
     y2 : out std_logic_vector(3 downto 0);
     z1:  out std_logic_vector(3 downto 0);
     z2:  out std_logic_vector(3 downto 0));
end component;
component pbclk  
port(a: in std_logic;
     b: in std_logic;
     c: in std_logic;
     cp: in std_logic;
     clk: out std_logic);
end component;
signal h1,h2,m1,m2,s1,s2,h_1,h_2,m_1,m_2,s_1,s_2: std_logic_vector(3 downto 0);
signal mx,en,tx,k1,k2,cp: std_logic;
signal day,day_y,clk_100: std_logic;
signal p1,p2:std_logic_vector(3 downto 0);
signal x1,x2,x:std_logic;
signal clk_1,clk_500:std_logic;
begin
 u1:kzyima port map(a,b,c,mx,en,tx,k1,k2);
 u2:xsxuanze port map(h1,h2,m1,m2,s1,s2,
                      h_1,h_2,m_1,m_2,s_1,s_2,
                      mx,en,
                      shi_h,shi_l,fen_h,fen_l,miao_h,miao_l);
 u3:sheding port map(clk_tiao2,tx,en,h_1,h_2,m_1,m_2,s_1,s_2);
 u4:bszz port map(clk,clk_500,d,h1,h2,m1,m2,s1,s2,p1,
                      h_1,h_2,m_1,m_2,kz);
 u5:shijian port map(cp,clk_tiao1,k1,k2,day,day_y,h1,h2,m1,m2,s1,s2);
 u6:pbclk port map(a,b,c,clk_1,cp);
 u7:fenpinqi port map(clk,clk_500,clk_1,p1,p2);
 end a;