📄 zhongbiao.rpt
字号:
(64) 126 H TFFE t 2 2 0 0 12 0 4 |fenpinqi:u7|counter100:u3|high13 (|fenpinqi:u7|counter100:u3|:17)
- 121 H TFFE t 2 2 0 0 10 0 4 |fenpinqi:u7|counter100:u3|high12 (|fenpinqi:u7|counter100:u3|:18)
(60) 115 H TFFE t 2 2 0 0 12 0 5 |fenpinqi:u7|counter100:u3|high11 (|fenpinqi:u7|counter100:u3|:19)
(61) 118 H TFFE t 2 2 0 0 8 0 5 |fenpinqi:u7|counter100:u3|high10 (|fenpinqi:u7|counter100:u3|:20)
- 132 I LCELL s t 0 0 0 3 2 0 18 |kzyima:u1|~231~1
- 65 E LCELL s t 1 0 1 3 2 0 18 |kzyima:u1|~232~1
- 133 I TFFE t 2 2 0 4 9 0 5 |sheding:u3|high13 (|sheding:u3|:29)
- 134 I TFFE t 2 2 0 4 8 0 6 |sheding:u3|high12 (|sheding:u3|:30)
- 68 E TFFE t 3 2 1 4 10 0 7 |sheding:u3|high11 (|sheding:u3|:31)
- 135 I TFFE t 2 2 0 4 6 0 7 |sheding:u3|high10 (|sheding:u3|:32)
(37) 72 E TFFE t 5 2 1 4 10 0 9 |sheding:u3|low13 (|sheding:u3|:33)
- 76 E TFFE t 3 2 1 4 10 0 9 |sheding:u3|low12 (|sheding:u3|:34)
- 130 I TFFE t 2 2 0 4 6 0 10 |sheding:u3|low11 (|sheding:u3|:35)
(70) 137 I TFFE t 2 2 0 4 2 0 9 |sheding:u3|low10 (|sheding:u3|:36)
(34) 80 E TFFE t 2 2 0 4 9 0 4 |sheding:u3|high23 (|sheding:u3|:37)
- 79 E TFFE t 2 2 0 4 10 0 5 |sheding:u3|high22 (|sheding:u3|:38)
- 71 E TFFE t 2 2 0 4 10 0 5 |sheding:u3|high21 (|sheding:u3|:39)
- 138 I TFFE t 2 2 0 4 6 0 6 |sheding:u3|high20 (|sheding:u3|:40)
- 140 I TFFE t 2 2 0 4 6 0 8 |sheding:u3|low23 (|sheding:u3|:41)
- 141 I TFFE t 2 2 0 4 4 0 8 |sheding:u3|low22 (|sheding:u3|:42)
(73) 144 I TFFE t 2 2 0 4 6 0 9 |sheding:u3|low21 (|sheding:u3|:43)
(67) 129 I TFFE t 2 2 0 4 2 0 9 |sheding:u3|low20 (|sheding:u3|:44)
- 143 I SOFT t 0 0 0 0 2 0 1 |shijian:u5|counter24:u3|LPM_ADD_SUB:181|addcore:adder|addcore:adder0|result_node1
(71) 139 I SOFT t 0 0 0 0 3 0 1 |shijian:u5|counter24:u3|LPM_ADD_SUB:181|addcore:adder|addcore:adder0|result_node2
(68) 131 I SOFT t 0 0 0 0 4 0 1 |shijian:u5|counter24:u3|LPM_ADD_SUB:181|addcore:adder|addcore:adder0|result_node3
- 109 G DFFE t 0 0 0 0 11 0 10 |shijian:u5|counter24:u3|low13 (|shijian:u5|counter24:u3|:13)
- 108 G DFFE t 4 4 0 4 11 0 11 |shijian:u5|counter24:u3|low12 (|shijian:u5|counter24:u3|:14)
(56) 107 G DFFE t 4 4 0 4 11 0 13 |shijian:u5|counter24:u3|low11 (|shijian:u5|counter24:u3|:15)
- 106 G TFFE t 4 4 0 4 2 0 12 |shijian:u5|counter24:u3|low10 (|shijian:u5|counter24:u3|:16)
- 98 G TFFE t 4 4 0 4 9 8 10 |shijian:u5|counter24:u3|high13 (|shijian:u5|counter24:u3|:17)
- 103 G TFFE t 4 4 0 4 8 0 7 |shijian:u5|counter24:u3|high12 (|shijian:u5|counter24:u3|:18)
- 100 G TFFE t 4 4 0 4 10 0 8 |shijian:u5|counter24:u3|high11 (|shijian:u5|counter24:u3|:19)
(57) 110 G TFFE t 4 4 0 4 6 0 8 |shijian:u5|counter24:u3|high10 (|shijian:u5|counter24:u3|:20)
(50) 94 F SOFT t 0 0 0 0 2 0 1 |shijian:u5|counter60:u1|LPM_ADD_SUB:181|addcore:adder|addcore:adder0|result_node1
- 87 F SOFT t 0 0 0 0 4 0 1 |shijian:u5|counter60:u1|LPM_ADD_SUB:181|addcore:adder|addcore:adder0|result_node3
- 159 J DFFE t 2 2 0 3 10 0 10 |shijian:u5|counter60:u1|:3
(44) 83 F DFFE t 2 2 0 3 6 0 12 |shijian:u5|counter60:u1|low13 (|shijian:u5|counter60:u1|:13)
(45) 86 F TFFE t 2 2 0 3 3 0 12 |shijian:u5|counter60:u1|low12 (|shijian:u5|counter60:u1|:14)
- 33 C DFFE t 2 2 0 3 6 0 14 |shijian:u5|counter60:u1|low11 (|shijian:u5|counter60:u1|:15)
- 81 F TFFE t 2 2 0 3 1 1 15 |shijian:u5|counter60:u1|low10 (|shijian:u5|counter60:u1|:16)
(81) 160 J TFFE t 2 2 0 3 8 0 7 |shijian:u5|counter60:u1|high13 (|shijian:u5|counter60:u1|:17)
- 150 J TFFE t 2 2 0 3 9 0 8 |shijian:u5|counter60:u1|high12 (|shijian:u5|counter60:u1|:18)
- 158 J TFFE t 2 2 0 3 9 0 8 |shijian:u5|counter60:u1|high11 (|shijian:u5|counter60:u1|:19)
- 157 J TFFE t 2 2 0 3 5 0 8 |shijian:u5|counter60:u1|high10 (|shijian:u5|counter60:u1|:20)
(69) 136 I SOFT t 0 0 0 0 2 0 1 |shijian:u5|counter60:u2|LPM_ADD_SUB:181|addcore:adder|addcore:adder0|result_node1
- 60 D SOFT t 0 0 0 0 4 0 1 |shijian:u5|counter60:u2|LPM_ADD_SUB:181|addcore:adder|addcore:adder0|result_node3
- 149 J DFFE t 4 4 0 4 10 0 9 |shijian:u5|counter60:u2|:3
- 49 D DFFE t 4 4 0 4 6 0 13 |shijian:u5|counter60:u2|low13 (|shijian:u5|counter60:u2|:13)
- 57 D TFFE t 4 4 0 4 3 0 13 |shijian:u5|counter60:u2|low12 (|shijian:u5|counter60:u2|:14)
- 50 D DFFE t 4 4 0 4 6 0 15 |shijian:u5|counter60:u2|low11 (|shijian:u5|counter60:u2|:15)
- 55 D TFFE t 4 4 0 4 1 0 15 |shijian:u5|counter60:u2|low10 (|shijian:u5|counter60:u2|:16)
(77) 153 J TFFE t 4 4 0 4 8 0 8 |shijian:u5|counter60:u2|high13 (|shijian:u5|counter60:u2|:17)
- 156 J TFFE t 4 4 0 4 9 0 9 |shijian:u5|counter60:u2|high12 (|shijian:u5|counter60:u2|:18)
- 154 J TFFE t 4 4 0 4 9 0 9 |shijian:u5|counter60:u2|high11 (|shijian:u5|counter60:u2|:19)
(80) 155 J TFFE t 4 4 0 4 5 0 10 |shijian:u5|counter60:u2|high10 (|shijian:u5|counter60:u2|:20)
(58) 112 G LCELL s t 0 0 0 3 0 0 8 |shijian:u5|xuanze:u4|~47~1
- 111 G SOFT s t 0 0 0 4 1 0 1 |shijian:u5|xuanze:u5|~53~1
- 97 G TFFE t 2 2 0 3 2 16 13 |xsxuanze:u2|cnt82 (|xsxuanze:u2|:67)
- 66 E TFFE t 2 2 0 3 1 16 14 |xsxuanze:u2|cnt81 (|xsxuanze:u2|:68)
- 82 F TFFE t 2 2 0 3 0 16 15 |xsxuanze:u2|cnt80 (|xsxuanze:u2|:69)
- 101 G SOFT s t 0 0 0 0 4 5 1 |xsxuanze:u2|~875~1
- 37 C SOFT s t 2 0 1 0 8 8 5 |xsxuanze:u2|~876~1
- 85 F SOFT s t 0 0 0 3 0 8 5 |xsxuanze:u2|~1562~1
(35) 78 E SOFT s t 3 2 1 3 7 8 5 |xsxuanze:u2|~1615~1
(75) 147 J SOFT s t 5 2 1 3 9 8 5 |xsxuanze:u2|~1620~1
(36) 75 E SOFT s t 3 2 1 3 7 8 5 |xsxuanze:u2|~1621~1
(52) 99 G SOFT s t 5 2 1 3 9 8 5 |xsxuanze:u2|~1626~1
- 73 E SOFT s t 3 2 1 3 7 8 5 |xsxuanze:u2|~1627~1
- 105 G SOFT s t 5 2 1 3 9 7 5 |xsxuanze:u2|~1632~1
- 74 E SOFT s t 3 2 1 3 7 7 5 |xsxuanze:u2|~1633~1
- 58 D SOFT s t 1 0 1 0 13 7 1 |xsxuanze:u2|~2191~1
- 52 D SOFT s t 1 1 0 0 13 7 1 |xsxuanze:u2|~2203~1
- 61 D SOFT s t 1 1 0 0 13 7 0 |xsxuanze:u2|~2215~1
- 63 D SOFT s t 1 1 0 0 7 4 1 |xsxuanze:u2|~2222~1
(27) 64 D SOFT s t 0 0 0 0 7 7 1 |xsxuanze:u2|~2227~1
- 53 D SOFT s t 1 0 1 0 13 2 0 |xsxuanze:u2|~2566~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\zhongbiao.rpt
zhongbiao
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC8 BT1
| +--- LC3 SG2
| | +- LC1 SG4
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B C D E F G H I J | Logic cells that feed LAB 'A':
Pin
83 -> - - - | - - - - - * - - - - | <-- clk
LC98 -> - * * | * * * * - - * * * - | <-- |shijian:u5|counter24:u3|high13
LC97 -> * * * | * * * * * - * * - * | <-- |xsxuanze:u2|cnt82
LC66 -> * * * | * * * * * - * * - * | <-- |xsxuanze:u2|cnt81
LC82 -> * * * | * * * * * - * * - * | <-- |xsxuanze:u2|cnt80
LC101-> - * * | * * - * - - - * - - | <-- |xsxuanze:u2|~875~1
LC37 -> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~876~1
LC85 -> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~1562~1
LC78 -> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~1615~1
LC147-> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~1620~1
LC75 -> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~1621~1
LC99 -> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~1626~1
LC73 -> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~1627~1
LC105-> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~1632~1
LC74 -> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~1633~1
LC58 -> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~2191~1
LC52 -> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~2203~1
LC61 -> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~2215~1
LC63 -> - * * | * - - * - - - - - - | <-- |xsxuanze:u2|~2222~1
LC64 -> - * * | * * * * - - - * - - | <-- |xsxuanze:u2|~2227~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\zhongbiao.rpt
zhongbiao
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------- LC24 |fenpinqi:u7|counter10:u2|LPM_ADD_SUB:146|addcore:adder|addcore:adder0|result_node1
| +----- LC18 |fenpinqi:u7|counter10:u2|temp3
| | +--- LC25 |fenpinqi:u7|counter10:u2|temp1
| | | +- LC19 SG1
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'B'
LC | | | | | A B C D E F G H I J | Logic cells that feed LAB 'B':
LC24 -> - - * - | - * - - - - - - - - | <-- |fenpinqi:u7|counter10:u2|LPM_ADD_SUB:146|addcore:adder|addcore:adder0|result_node1
LC18 -> - * * - | - * - - - - - * - - | <-- |fenpinqi:u7|counter10:u2|temp3
LC25 -> * * * - | - * - - - - - * - - | <-- |fenpinqi:u7|counter10:u2|temp1
Pin
83 -> - - - - | - - - - - * - - - - | <-- clk
LC120-> - * - - | - * - - - - - - - - | <-- |fenpinqi:u7|counter10:u2|LPM_ADD_SUB:146|addcore:adder|addcore:adder0|result_node3
LC113-> - * * - | - * - - - - - * - - | <-- |fenpinqi:u7|counter10:u2|temp2
LC84 -> * * * - | - * - - - - - * - - | <-- |fenpinqi:u7|counter10:u2|temp0
LC98 -> - - - * | * * * * - - * * * - | <-- |shijian:u5|counter24:u3|high13
LC97 -> - - - * | * * * * * - * * - * | <-- |xsxuanze:u2|cnt82
LC66 -> - - - * | * * * * * - * * - * | <-- |xsxuanze:u2|cnt81
LC82 -> - - - * | * * * * * - * * - * | <-- |xsxuanze:u2|cnt80
LC101-> - - - * | * * - * - - - * - - | <-- |xsxuanze:u2|~875~1
LC37 -> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~876~1
LC85 -> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~1562~1
LC78 -> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~1615~1
LC147-> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~1620~1
LC75 -> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~1621~1
LC99 -> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~1626~1
LC73 -> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~1627~1
LC105-> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~1632~1
LC74 -> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~1633~1
LC58 -> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~2191~1
LC52 -> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~2203~1
LC61 -> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~2215~1
LC64 -> - - - * | * * * * - - - * - - | <-- |xsxuanze:u2|~2227~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\zhongbiao.rpt
zhongbiao
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------- LC43 BT0
| +------- LC38 SG0
| | +----- LC35 SG3
| | | +--- LC33 |shijian:u5|counter60:u1|low11
| | | | +- LC37 |xsxuanze:u2|~876~1
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'C'
LC | | | | | | A B C D E F G H I J | Logic cells that feed LAB 'C':
LC33 -> - - - * - | - - * - - * * - - * | <-- |shijian:u5|counter60:u1|low11
LC37 -> - * * - - | * * * * - - - * - - | <-- |xsxuanze:u2|~876~1
Pin
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -