📄 zhongbiao.rpt
字号:
G G T o N C o N N N N l N E E C I E E E
4 2 1 1 D . 2 d T D D D k D D D . O D D D
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/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
RESERVED | 12 74 | c
VCCIO | 13 73 | RESERVED
#TDI | 14 72 | GND
RESERVED | 15 71 | #TDO
a | 16 70 | RESERVED
SG1 | 17 69 | RESERVED
b | 18 68 | RESERVED
GND | 19 67 | RESERVED
BT0 | 20 66 | VCCIO
RESERVED | 21 65 | SG6
RESERVED | 22 EPM7160SLC84-6 64 | RESERVED
#TMS | 23 63 | RESERVED
SG0 | 24 62 | #TCK
SG3 | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
RESERVED | 27 59 | GND
SG7 | 28 58 | RESERVED
BT5 | 29 57 | RESERVED
SG5 | 30 56 | RESERVED
BT7 | 31 55 | BT2
GND | 32 54 | BT3
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
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B R R R R V N R B G V R R N G k R R R R V
T E E E E C . E T N C E E . N z E E E E C
6 S S S S C C S 4 D C S S C D S S S S C
E E E E I . E I E E . E E E E I
R R R R O R N R R R R R R O
V V V V V T V V V V V V
E E E E E E E E E E E
D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\zhongbiao.rpt
zhongbiao
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 6/ 6(100%) 16/16(100%) 19/36( 52%)
B: LC17 - LC32 4/16( 25%) 4/ 6( 66%) 16/16(100%) 24/36( 66%)
C: LC33 - LC48 5/16( 31%) 4/ 6( 66%) 16/16(100%) 31/36( 86%)
D: LC49 - LC64 16/16(100%) 5/ 6( 83%) 16/16(100%) 30/36( 83%)
E: LC65 - LC80 16/16(100%) 1/ 6( 16%) 16/16(100%) 33/36( 91%)
F: LC81 - LC96 16/16(100%) 1/ 6( 16%) 6/16( 37%) 22/36( 61%)
G: LC97 - LC112 16/16(100%) 2/ 6( 33%) 14/16( 87%) 29/36( 80%)
H: LC113 - LC128 14/16( 87%) 2/ 6( 33%) 9/16( 56%) 33/36( 91%)
I: LC129 - LC144 16/16(100%) 1/ 6( 16%) 16/16(100%) 31/36( 86%)
J: LC145 - LC160 14/16( 87%) 1/ 6( 16%) 12/16( 75%) 33/36( 91%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 27/60 ( 45%)
Total logic cells used: 120/160 ( 75%)
Total shareable expanders used: 115/160 ( 71%)
Total Turbo logic cells used: 120/160 ( 75%)
Total shareable expanders not available (n/a): 22/160 ( 13%)
Average fan-in: 9.13
Total fan-in: 1096
Total input pins required: 7
Total fast input logic cells required: 0
Total output pins required: 17
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 120
Total flipflops required: 62
Total product terms required: 443
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 95
Synthesized logic cells: 28/ 160 ( 17%)
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\zhongbiao.rpt
zhongbiao
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
16 (24) (B) INPUT 0 0 0 0 0 0 56 a
18 (17) (B) INPUT 0 0 0 0 0 0 56 b
74 (145) (J) INPUT 0 0 0 0 0 0 56 c
83 - - INPUT G 0 0 0 0 0 1 0 clk
8 (9) (A) INPUT 0 0 0 0 0 0 17 clk_tiao1
5 (11) (A) INPUT 0 0 0 0 0 0 16 clk_tiao2
4 (16) (A) INPUT 0 0 0 0 0 1 0 d
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\zhongbiao.rpt
zhongbiao
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
20 43 C OUTPUT t 0 0 0 0 3 0 0 BT0
9 8 A OUTPUT t 0 0 0 0 3 0 0 BT1
55 104 G OUTPUT t 0 0 0 0 3 0 0 BT2
54 102 G OUTPUT t 0 0 0 0 3 0 0 BT3
41 67 E OUTPUT t 0 0 0 0 3 0 0 BT4
29 59 D OUTPUT t 0 0 0 0 3 0 0 BT5
33 51 D OUTPUT t 0 0 0 0 3 0 0 BT6
31 54 D OUTPUT t 0 0 0 0 3 0 0 BT7
48 88 F OUTPUT t 2 1 0 2 10 0 0 kz
24 38 C OUTPUT t 8 8 0 0 16 0 0 SG0
17 19 B OUTPUT t 16 0 0 0 18 0 0 SG1
10 3 A OUTPUT t 7 2 1 0 19 0 0 SG2
25 35 C OUTPUT t 12 8 0 0 18 0 0 SG3
11 1 A OUTPUT t 11 2 1 0 19 0 0 SG4
30 56 D OUTPUT t 10 2 1 0 19 0 0 SG5
65 123 H OUTPUT t 7 1 1 0 18 0 0 SG6
28 62 D OUTPUT t 2 2 0 0 14 0 0 SG7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\zhongbiao.rpt
zhongbiao
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 95 F SOFT s t 1 1 0 0 3 1 0 |bszz:u4|baoshiqi:u2|~73~1
- 148 J SOFT s t 1 1 0 0 17 1 0 |bszz:u4|baoshiqi:u2|~79~1
(76) 152 J SOFT s t 1 1 0 0 17 1 0 |bszz:u4|baoshiqi:u2|~81~1
- 142 I SOFT s t 14 0 1 0 21 1 3 |bszz:u4|baoshi:u1|~180~1
(40) 70 E SOFT s t 1 0 1 0 6 0 1 |bszz:u4|baoshi:u1|~180~2
- 69 E SOFT s t 1 0 1 0 6 0 1 |bszz:u4|baoshi:u1|~180~3
- 77 E SOFT s t 1 0 1 0 6 0 1 |bszz:u4|baoshi:u1|~180~4
- 151 J SOFT s t 0 0 0 0 20 1 1 |bszz:u4|baoshi:u1|~400~1
- 90 F SOFT t 0 0 0 0 2 0 1 |fenpinqi:u7|counter2:u1|LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node1
- 93 F SOFT t 0 0 0 0 4 0 1 |fenpinqi:u7|counter2:u1|LPM_ADD_SUB:99|addcore:adder|addcore:adder0|result_node3
- 89 F DFFE + t 0 0 0 0 5 1 3 |fenpinqi:u7|counter2:u1|temp3 (|fenpinqi:u7|counter2:u1|:4)
(49) 91 F TFFE + t 0 0 0 0 2 1 3 |fenpinqi:u7|counter2:u1|temp2 (|fenpinqi:u7|counter2:u1|:5)
- 92 F DFFE + t 0 0 0 0 5 1 5 |fenpinqi:u7|counter2:u1|temp1 (|fenpinqi:u7|counter2:u1|:6)
(51) 96 F TFFE + t 0 0 0 0 0 1 5 |fenpinqi:u7|counter2:u1|temp0 (|fenpinqi:u7|counter2:u1|:7)
(16) 24 B SOFT t 0 0 0 0 2 0 1 |fenpinqi:u7|counter10:u2|LPM_ADD_SUB:146|addcore:adder|addcore:adder0|result_node1
(62) 120 H SOFT t 0 0 0 0 4 0 1 |fenpinqi:u7|counter10:u2|LPM_ADD_SUB:146|addcore:adder|addcore:adder0|result_node3
- 18 B DFFE + t 0 0 0 0 5 0 12 |fenpinqi:u7|counter10:u2|temp3 (|fenpinqi:u7|counter10:u2|:4)
- 113 H TFFE + t 0 0 0 0 2 0 12 |fenpinqi:u7|counter10:u2|temp2 (|fenpinqi:u7|counter10:u2|:5)
(15) 25 B DFFE + t 0 0 0 0 5 0 14 |fenpinqi:u7|counter10:u2|temp1 (|fenpinqi:u7|counter10:u2|:6)
- 84 F TFFE + t 0 0 0 0 0 0 14 |fenpinqi:u7|counter10:u2|temp0 (|fenpinqi:u7|counter10:u2|:7)
- 127 H SOFT t 0 0 0 0 2 0 1 |fenpinqi:u7|counter100:u3|LPM_ADD_SUB:181|addcore:adder|addcore:adder0|result_node1
- 122 H SOFT t 0 0 0 0 4 0 1 |fenpinqi:u7|counter100:u3|LPM_ADD_SUB:181|addcore:adder|addcore:adder0|result_node3
- 125 H DFFE t 2 2 0 0 13 0 10 |fenpinqi:u7|counter100:u3|:3
- 124 H DFFE t 2 2 0 0 9 0 8 |fenpinqi:u7|counter100:u3|low13 (|fenpinqi:u7|counter100:u3|:13)
(63) 128 H TFFE t 2 2 0 0 6 0 8 |fenpinqi:u7|counter100:u3|low12 (|fenpinqi:u7|counter100:u3|:14)
- 114 H DFFE t 2 2 0 0 9 0 10 |fenpinqi:u7|counter100:u3|low11 (|fenpinqi:u7|counter100:u3|:15)
- 116 H TFFE t 2 2 0 0 4 0 10 |fenpinqi:u7|counter100:u3|low10 (|fenpinqi:u7|counter100:u3|:16)
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