baoshi.rpt
来自「VHDL的数字电子钟程序」· RPT 代码 · 共 639 行 · 第 1/2 页
RPT
639 行
Project Information d:\nie_x\vhdl\zhongbiao\baoshi.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/12/2007 10:50:39
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
BAOSHI
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
baoshi EPM7064SLC84-5 44 3 0 8 8 12 %
User Pins: 44 3 0
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\baoshi.rpt
baoshi
***** Logic for device 'baoshi' compiled without errors.
Device: EPM7064SLC84-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R
E E E E E
V S S S S S
C E E E V E E
m p p p p s s C R R R C R R
_ _ _ _ G _ _ _ I G G G G G V V V C V V h
l h h h N h h h N N N N N N E E E I E E 1
3 0 1 2 D 3 0 1 T D D D D D D D D O D D 0
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
m_l2 | 12 74 | RESERVED
VCCIO | 13 73 | f23
#TDI | 14 72 | GND
m_l1 | 15 71 | #TDO
m_h3 | 16 70 | f22
f_l0 | 17 69 | x_di
f_l1 | 18 68 | h12
GND | 19 67 | RESERVED
m_l0 | 20 66 | VCCIO
s_l1 | 21 65 | RESERVED
h21 | 22 EPM7064SLC84-5 64 | x_du
#TMS | 23 63 | RESERVED
f_h1 | 24 62 | #TCK
m_h2 | 25 61 | RESERVED
VCCIO | 26 60 | h13
s_l3 | 27 59 | GND
f_h2 | 28 58 | f_h0
f_h3 | 29 57 | h20
s_l2 | 30 56 | RESERVED
s_l0 | 31 55 | h22
GND | 32 54 | h23
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
f f s f f V f s f G V m m h G x f f R R V
_ _ _ 1 1 C 1 _ 1 N C _ _ 1 N _ 2 2 E E C
l l h 0 1 C 2 h 3 D C h h 1 D n 0 1 S S C
2 3 3 I 2 I 1 0 z E E I
O N R R O
T V V
E E
D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\baoshi.rpt
baoshi
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 1/16( 6%) 16/16(100%) 1/16( 6%) 6/36( 16%)
B: LC17 - LC32 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 1/16( 6%) 12/16( 75%) 9/16( 56%) 17/36( 47%)
D: LC49 - LC64 6/16( 37%) 7/16( 43%) 3/16( 18%) 32/36( 88%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 51/64 ( 79%)
Total logic cells used: 8/64 ( 12%)
Total shareable expanders used: 8/64 ( 12%)
Total Turbo logic cells used: 8/64 ( 12%)
Total shareable expanders not available (n/a): 5/64 ( 7%)
Average fan-in: 10.00
Total fan-in: 80
Total input pins required: 44
Total fast input logic cells required: 0
Total output pins required: 3
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 8
Total flipflops required: 0
Total product terms required: 37
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 8
Synthesized logic cells: 5/ 64 ( 7%)
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\baoshi.rpt
baoshi
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
58 (45) (C) INPUT 0 0 0 0 0 1 3 f_h0
24 (31) (B) INPUT 0 0 0 0 0 1 2 f_h1
28 (28) (B) INPUT 0 0 0 0 0 1 2 f_h2
29 (27) (B) INPUT 0 0 0 0 0 1 2 f_h3
17 (5) (A) INPUT 0 0 0 0 0 2 1 f_l0
18 (4) (A) INPUT 0 0 0 0 0 2 1 f_l1
33 (24) (B) INPUT 0 0 0 0 0 1 2 f_l2
34 (23) (B) INPUT 0 0 0 0 0 1 2 f_l3
36 (21) (B) INPUT 0 0 0 0 0 0 2 f10
37 (20) (B) INPUT 0 0 0 0 0 0 1 f11
39 (19) (B) INPUT 0 0 0 0 0 0 1 f12
41 (17) (B) INPUT 0 0 0 0 0 0 1 f13
49 (37) (C) INPUT 0 0 0 0 0 1 0 f20
50 (38) (C) INPUT 0 0 0 0 0 1 0 f21
70 (55) (D) INPUT 0 0 0 0 0 0 1 f22
73 (57) (D) INPUT 0 0 0 0 0 0 1 f23
75 (59) (D) INPUT 0 0 0 0 0 1 0 h10
46 (35) (C) INPUT 0 0 0 0 0 1 0 h11
68 (53) (D) INPUT 0 0 0 0 0 1 0 h12
60 (46) (C) INPUT 0 0 0 0 0 1 0 h13
57 (44) (C) INPUT 0 0 0 0 0 0 1 h20
22 (1) (A) INPUT 0 0 0 0 0 0 2 h21
55 (42) (C) INPUT 0 0 0 0 0 0 1 h22
54 (41) (C) INPUT 0 0 0 0 0 0 1 h23
45 (34) (C) INPUT 0 0 0 0 0 1 1 m_h0
44 (33) (C) INPUT 0 0 0 0 0 1 1 m_h1
25 (30) (B) INPUT 0 0 0 0 0 1 1 m_h2
16 (6) (A) INPUT 0 0 0 0 0 1 1 m_h3
20 (3) (A) INPUT 0 0 0 0 0 2 1 m_l0
15 (7) (A) INPUT 0 0 0 0 0 1 1 m_l1
12 (9) (A) INPUT 0 0 0 0 0 1 1 m_l2
11 (10) (A) INPUT 0 0 0 0 0 1 1 m_l3
10 (11) (A) INPUT 0 0 0 0 0 0 1 p_h0
9 (12) (A) INPUT 0 0 0 0 0 0 1 p_h1
8 (13) (A) INPUT 0 0 0 0 0 0 1 p_h2
6 (14) (A) INPUT 0 0 0 0 0 0 1 p_h3
5 (15) (A) INPUT 0 0 0 0 0 1 0 s_h0
4 (16) (A) INPUT 0 0 0 0 0 1 0 s_h1
40 (18) (B) INPUT 0 0 0 0 0 1 0 s_h2
35 (22) (B) INPUT 0 0 0 0 0 1 0 s_h3
31 (25) (B) INPUT 0 0 0 0 0 0 1 s_l0
21 (2) (A) INPUT 0 0 0 0 0 0 2 s_l1
30 (26) (B) INPUT 0 0 0 0 0 0 1 s_l2
27 (29) (B) INPUT 0 0 0 0 0 0 1 s_l3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\baoshi.rpt
baoshi
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
69 54 D OUTPUT t 0 0 0 16 1 0 0 x_di
64 50 D OUTPUT t 0 0 0 0 2 0 0 x_du
48 36 C OUTPUT t 9 0 1 13 4 2 0 x_nz
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\baoshi.rpt
baoshi
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(68) 53 D SOFT s t 1 0 1 6 0 1 0 ~182~2
(65) 51 D SOFT s t 1 0 1 6 0 1 0 ~182~3
(63) 49 D SOFT s t 1 0 1 6 0 1 0 ~182~4
(22) 1 A SOFT s t 1 0 1 6 0 1 0 ~182~5
(67) 52 D SOFT s t 0 0 0 20 0 1 0 ~511~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\baoshi.rpt
baoshi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC1 ~182~5
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B C D | Logic cells that feed LAB 'A':
Pin
22 -> * | * - - * | <-- h21
55 -> * | * - - - | <-- h22
54 -> * | * - - - | <-- h23
21 -> * | * - - * | <-- s_l1
30 -> * | * - - - | <-- s_l2
27 -> * | * - - - | <-- s_l3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\baoshi.rpt
baoshi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+- LC36 x_nz
|
| Other LABs fed by signals
| that feed LAB 'C'
LC | | A B C D | Logic cells that feed LAB 'C':
Pin
17 -> * | - - * * | <-- f_l0
18 -> * | - - * * | <-- f_l1
49 -> * | - - * - | <-- f20
50 -> * | - - * - | <-- f21
75 -> * | - - * - | <-- h10
46 -> * | - - * - | <-- h11
68 -> * | - - * - | <-- h12
60 -> * | - - * - | <-- h13
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?