baoshi.rpt
来自「VHDL的数字电子钟程序」· RPT 代码 · 共 639 行 · 第 1/2 页
RPT
639 行
20 -> * | - - * * | <-- m_l0
5 -> * | - - * - | <-- s_h0
4 -> * | - - * - | <-- s_h1
40 -> * | - - * - | <-- s_h2
35 -> * | - - * - | <-- s_h3
LC53 -> * | - - * - | <-- ~182~2
LC51 -> * | - - * - | <-- ~182~3
LC49 -> * | - - * - | <-- ~182~4
LC1 -> * | - - * - | <-- ~182~5
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\baoshi.rpt
baoshi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+----------- LC54 x_di
| +--------- LC50 x_du
| | +------- LC53 ~182~2
| | | +----- LC51 ~182~3
| | | | +--- LC49 ~182~4
| | | | | +- LC52 ~511~1
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'D'
LC | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC52 -> - * - - - - | - - - * | <-- ~511~1
Pin
58 -> * - * * - * | - - - * | <-- f_h0
24 -> * - - * - * | - - - * | <-- f_h1
28 -> * - - * - * | - - - * | <-- f_h2
29 -> * - - - * * | - - - * | <-- f_h3
17 -> * - - - - * | - - * * | <-- f_l0
18 -> * - - - - * | - - * * | <-- f_l1
33 -> * - * - - * | - - - * | <-- f_l2
34 -> * - * - - * | - - - * | <-- f_l3
36 -> - - * * - - | - - - * | <-- f10
37 -> - - - * - - | - - - * | <-- f11
39 -> - - - * - - | - - - * | <-- f12
41 -> - - - - * - | - - - * | <-- f13
70 -> - - * - - - | - - - * | <-- f22
73 -> - - * - - - | - - - * | <-- f23
57 -> - - - - * - | - - - * | <-- h20
22 -> - - - - * - | * - - * | <-- h21
45 -> * - - - - * | - - - * | <-- m_h0
44 -> * - - - - * | - - - * | <-- m_h1
25 -> * - - - - * | - - - * | <-- m_h2
16 -> * - - - - * | - - - * | <-- m_h3
20 -> * - - - - * | - - * * | <-- m_l0
15 -> * - - - - * | - - - * | <-- m_l1
12 -> * - - - - * | - - - * | <-- m_l2
11 -> * - - - - * | - - - * | <-- m_l3
10 -> - - - - - * | - - - * | <-- p_h0
9 -> - - - - - * | - - - * | <-- p_h1
8 -> - - - - - * | - - - * | <-- p_h2
6 -> - - - - - * | - - - * | <-- p_h3
31 -> - - - - * - | - - - * | <-- s_l0
21 -> - - - - * - | * - - * | <-- s_l1
LC36 -> * * - - - - | - - - * | <-- x_nz
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\nie_x\vhdl\zhongbiao\baoshi.rpt
baoshi
** EQUATIONS **
f_h0 : INPUT;
f_h1 : INPUT;
f_h2 : INPUT;
f_h3 : INPUT;
f_l0 : INPUT;
f_l1 : INPUT;
f_l2 : INPUT;
f_l3 : INPUT;
f10 : INPUT;
f11 : INPUT;
f12 : INPUT;
f13 : INPUT;
f20 : INPUT;
f21 : INPUT;
f22 : INPUT;
f23 : INPUT;
h10 : INPUT;
h11 : INPUT;
h12 : INPUT;
h13 : INPUT;
h20 : INPUT;
h21 : INPUT;
h22 : INPUT;
h23 : INPUT;
m_h0 : INPUT;
m_h1 : INPUT;
m_h2 : INPUT;
m_h3 : INPUT;
m_l0 : INPUT;
m_l1 : INPUT;
m_l2 : INPUT;
m_l3 : INPUT;
p_h0 : INPUT;
p_h1 : INPUT;
p_h2 : INPUT;
p_h3 : INPUT;
s_h0 : INPUT;
s_h1 : INPUT;
s_h2 : INPUT;
s_h3 : INPUT;
s_l0 : INPUT;
s_l1 : INPUT;
s_l2 : INPUT;
s_l3 : INPUT;
-- Node name is 'x_di'
-- Equation name is 'x_di', location is LC054, type is output.
x_di = LCELL( _EQ001 $ GND);
_EQ001 = f_h0 & !f_h1 & f_h2 & !f_h3 & f_l0 & !f_l1 & !f_l2 & f_l3 &
m_h0 & !m_h1 & m_h2 & !m_h3 & m_l0 & !m_l1 & !m_l2 & m_l3 &
!x_nz;
-- Node name is 'x_du'
-- Equation name is 'x_du', location is LC050, type is output.
x_du = LCELL( _EQ002 $ GND);
_EQ002 = _LC052 & !x_nz;
-- Node name is 'x_nz'
-- Equation name is 'x_nz', location is LC036, type is output.
x_nz = LCELL( _EQ003 $ _EQ004);
_EQ003 = f_l0 & !f20 & !_LC001 & !_LC049 & !_LC051 & !_LC053 & !m_l0 &
_X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &
_X008
# !f_l0 & f20 & !_LC001 & !_LC049 & !_LC051 & !_LC053 & !m_l0 &
_X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &
_X008
# f_l1 & !f21 & !_LC001 & !_LC049 & !_LC051 & !_LC053 & !m_l0 &
_X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &
_X008
# !f_l1 & f21 & !_LC001 & !_LC049 & !_LC051 & !_LC053 & !m_l0 &
_X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &
_X008;
_X001 = EXP( h11 & !s_h1);
_X002 = EXP(!h10 & s_h0);
_X003 = EXP( h10 & !s_h0);
_X004 = EXP( h13 & !s_h3);
_X005 = EXP(!h13 & s_h3);
_X006 = EXP( h12 & !s_h2);
_X007 = EXP(!h12 & s_h2);
_X008 = EXP(!h11 & s_h1);
_EQ004 = !_LC001 & !_LC049 & !_LC051 & !_LC053 & !m_l0 & _X001 & _X002 &
_X003 & _X004 & _X005 & _X006 & _X007 & _X008;
_X001 = EXP( h11 & !s_h1);
_X002 = EXP(!h10 & s_h0);
_X003 = EXP( h10 & !s_h0);
_X004 = EXP( h13 & !s_h3);
_X005 = EXP(!h13 & s_h3);
_X006 = EXP( h12 & !s_h2);
_X007 = EXP(!h12 & s_h2);
_X008 = EXP(!h11 & s_h1);
-- Node name is '~182~2'
-- Equation name is '~182~2', location is LC053, type is buried.
-- synthesized logic cell
_LC053 = LCELL( _EQ005 $ GND);
_EQ005 = f_l2 & !f22
# !f_l2 & f22
# f_l3 & !f23
# !f_l3 & f23
# f_h0 & !f10;
-- Node name is '~182~3'
-- Equation name is '~182~3', location is LC051, type is buried.
-- synthesized logic cell
_LC051 = LCELL( _EQ006 $ GND);
_EQ006 = !f_h0 & f10
# f_h1 & !f11
# !f_h1 & f11
# f_h2 & !f12
# !f_h2 & f12;
-- Node name is '~182~4'
-- Equation name is '~182~4', location is LC049, type is buried.
-- synthesized logic cell
_LC049 = LCELL( _EQ007 $ GND);
_EQ007 = f_h3 & !f13
# !f_h3 & f13
# !h20 & s_l0
# h20 & !s_l0
# !h21 & s_l1;
-- Node name is '~182~5'
-- Equation name is '~182~5', location is LC001, type is buried.
-- synthesized logic cell
_LC001 = LCELL( _EQ008 $ GND);
_EQ008 = h21 & !s_l1
# !h22 & s_l2
# h22 & !s_l2
# !h23 & s_l3
# h23 & !s_l3;
-- Node name is '~511~1'
-- Equation name is '~511~1', location is LC052, type is buried.
-- synthesized logic cell
_LC052 = LCELL( _EQ009 $ GND);
_EQ009 = f_h0 & !f_h1 & f_h2 & !f_h3 & f_l0 & !f_l1 & !f_l2 & f_l3 &
m_h0 & !m_h1 & m_h2 & !m_h3 & !m_l0 & !m_l1 & !m_l2 & !p_h0 &
!p_h1 & !p_h2 & !p_h3
# f_h0 & !f_h1 & f_h2 & !f_h3 & f_l0 & !f_l1 & !f_l2 & f_l3 &
m_h0 & !m_h1 & m_h2 & !m_h3 & !m_l0 & !m_l3 & !p_h0 & !p_h1 &
!p_h2 & !p_h3;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\nie_x\vhdl\zhongbiao\baoshi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,995K
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?