baoshi.vhd

VHDL的数字电子钟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity baoshi is
port(s_h: in std_logic_vector(3 downto 0);
     s_l: in std_logic_vector(3 downto 0);
     f_h: in std_logic_vector(3 downto 0);
     f_l: in std_logic_vector(3 downto 0);
     m_h: in std_logic_vector(3 downto 0);
     m_l: in std_logic_vector(3 downto 0);
     p_h: in std_logic_vector(3 downto 0);
     h1 : in std_logic_vector(3 downto 0);
     h2 : in std_logic_vector(3 downto 0);
     f1 : in std_logic_vector(3 downto 0);
     f2 : in std_logic_vector(3 downto 0);
     x_du: out std_logic;
     x_di: out std_logic;
     x_nz: out std_logic);
end baoshi;
architecture a of baoshi is
signal en,t:std_logic;
signal o1,o2,output:std_logic;
begin
   t<=m_l(0);
p1:process(en)
  begin
  if((s_h=h1 and s_l=h2) and (f_h=f1 and f_l=f2))then
    if(t='0')then output<='1';
     else output<='0';
    end if;
     else output<='0';
   end if;
 end process;
p2:process(en)
  begin
  if((f_h="0101" and f_l="1001") and m_h="0101")then
     if(p_h="0000")then
       if(m_l="0000")then o1<='1';
        elsif(m_l="0010")then o1<='1';
        elsif(m_l="0100")then o1<='1';
        elsif(m_l="0110")then o1<='1';
        elsif(m_l="1000")then o1<='1';
        else o1<='0';
       end if;
       else o1<='0';
      end if;
     else o1<='0';
   end if;
 end process;
p3:process(en)
  begin
  if((f_h="0101" and f_l="1001") and (m_h="0101" and m_l="1001"))then
      o2<='1';
  else o2<='0';
  end if;
 end process;
p4:process(en)
   begin
    x_nz<=output;
    if(output='1')then x_du<='0'; x_di<='0';
     else x_du<=o1; x_di<=o2;
    end if;
   end process;
end a;