fenpinqi.vhd

VHDL的数字电子钟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;

entity fenpinqi is
port(clk:in std_logic;
     clk_500hz:out std_logic;
     clk_1hz:out std_logic;
     pm_h: out std_logic_vector(3 downto 0);
     pm_l:  out std_logic_vector(3 downto 0));
end fenpinqi;
architecture a of fenpinqi is
component counter2 
port(clk: in std_logic;
      en: in std_logic;
      output: out std_logic);
end component;
component counter10  
port(clk: in std_logic;
      en: in std_logic;
      output: out std_logic);
end component;
component counter100  
port(clk: in std_logic;
      en: in std_logic;
      co :out std_logic;
      high: out std_logic_vector(3 downto 0);
      low:  out std_logic_vector(3 downto 0));
end component;
signal temp,clk_100hz:std_logic;
begin
 temp<='0';
 u1:counter2 port map(clk,temp,clk_500hz);
 u2:counter10 port map(clk,temp,clk_100hz);
 u3:counter100 port map(clk_100hz,temp,clk_1hz,pm_h,pm_l);
end a;
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