kzyima.vhd

VHDL的数字电子钟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity kzyima is
port(a: in std_logic;
     b: in std_logic;
     c: in std_logic;
     mx: out std_logic;
     en: out std_logic;
     tx: out std_logic;
     k1: out std_logic;
     k2: out std_logic);
end kzyima;
architecture a of kzyima is
begin
 process(a,b,c)
  begin
   if((a='0' and b='0') and c='0')then 
      mx<='0'; en<='0'; k1<='0'; k2<='0';
   elsif((a='0' and b='0') and c='1')then 
      mx<='0'; en<='0'; k1<='1'; k2<='0';
   elsif((a='0' and b='1') and c='0')then 
      mx<='0'; en<='0'; k1<='0'; k2<='1';
   elsif((a='1' and b='0') and c='0')then 
      mx<='1'; en<='0'; tx<='0'; k1<='0'; k2<='0';
   elsif((a='1' and b='0') and c='1')then 
      mx<='1'; en<='1'; tx<='0'; k1<='0'; k2<='0';
   elsif((a='1' and b='1') and c='0')then 
      mx<='1'; en<='1'; tx<='1'; k1<='0'; k2<='0';
   else mx<='0'; en<='0'; k1<='0'; k2<='0';
   end if;
end process;
end a;