readme.txt

system verilog design book examples

26 Jul 2004

This directory contains code examples and snippets from the book
"SystemVerilog for Design", by Stuart Sutherland, Simon Davidmann,
and Peter Flake.  Book copyright: 2003, Kluwer Academic Publishers,
Norwell, MA, USA www.wkap.il, ISBN: 0-4020-7530-8.

The examples are provided as a courtesy to readers of the book who
wish to try out the examples.  Each example includes a bare bones
test in order to verify that the example compiles, loads and runs
in simulation.  The rudimentary tests are NOT comprehensive, and
are NOT intended to be used to verify proper implementation of
SystemVerilog by software tools.  The intent of the simple tests
is to show the that each example is syntactically and
semantically correct.

All examples are copyrighted by Sutherland HDL, Inc.  The examples
may be used and distributed without restriction, provided that the
entire comment block of each example is included with the example.

CAVEATS:
a) These examples are a subset of SystemVerilog, focussing on the
extensions to Verilog that either are synthesizable, or are expected
to be synthesizable, using current RTL synthesis technologies.

b) The examples are NOT intended to be a validation suite for
SystemVerilog tools.  The examples are only meant to illustrate
how specific SystemVerilog features might be used.

c) Some of examples are not fully tested, as the examples were
developed before EDA tools were available to verify all examples.

d) The examples include rudimentary test code for use with simulation
tools.  Some modification to the examples may be required in order
to try the examples with other types of tools, such as conditionally
removing the test code for synthesis compilers.

e) Simulation results and expected results are displayed for visual
verification.  The rudimentary tests do not include automated
self-checking.

f) The expected results of the examples are based on the author's
interpretation of the SystemVerilog standard.  There are currently no
SystemVerilog validation suites with which to verify that the
expected results are correct.

ERRATA:
A list of known errata in the book and book examples is available at
www.sutherland-hdl.com

REPORTING ERRORS OR SUGGESTIONS:
The book authors would like to hear about any problems or errors you
encounter with these examples.  Suggestions on how to improve any
examples are also welcome.  Please send your feedback to:
  Stuart Sutherland
  [e-mail]