06.05.00_snippet-2.v

system verilog design book examples

/**********************************************************************
 * Using disable to return early from a task
 * (Verilog style code)
 *
 * Author: Stuart Sutherland
 *
 * (c) Copyright 2003, Sutherland HDL, Inc. *** ALL RIGHTS RESERVED ***
 * www.sutherland-hdl.com
 *
 * Used with permission in the book, "SystemVerilog for Design"
 *  By Stuart Sutherland, Simon Davidmann, and Peter Flake.
 *  Book copyright: 2003, Kluwer Academic Publishers, Norwell, MA, USA
 *  www.wkap.il, ISBN: 0-4020-7530-8
 *
 * Revision History:
 *   1.00 15 Dec 2003 -- original code, as included in book
 *   1.01 10 Jul 2004 -- cleaned up comments, added expected results
 *                       to output messages
 *
 * Caveat: Expected results displayed for this code example are based
 * on an interpretation of the SystemVerilog 3.1 standard by the code
 * author or authors.  At the time of writing, official SystemVerilog
 * validation suites were not available to validate the example.
 *
 * RIGHT TO USE: This code example, or any portion thereof, may be
 * used and distributed without restriction, provided that this entire
 * comment block is included with the example.
 *
 * DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
 * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
 * TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
 * EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
 * INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
 * USE OF THIS CODE.
 *********************************************************************/

module test;
  reg [63:0] result;

  task add_to_max (input  [ 5:0] max,
                   output [63:0] result);
    integer i;
    begin
      result = 1;
      if (max == 0)
        disable add_to_max; // exit task
      for (i=1; i<=63; i=i+1) begin
        result = result + result;
        if (i == max)
          disable add_to_max; // exit task
      end
    end
  endtask

  initial begin
    add_to_max(4, result);
    $display("\n for max=4, result=%0d (expect 16)", result);
    add_to_max(0, result);
    $display(" for max=0, result=%0d (expect 1)", result);
    add_to_max(12, result);
    $display(" for max=12, result=%0d (expect 4096)\n", result);
    $finish;
  end
endmodule