04.03.06_snippet-1.sv

system verilog design book examples

/**********************************************************************
 * Assigning packed arrays to packed arrays (legal)
 *
 * Author: Stuart Sutherland
 *
 * (c) Copyright 2003, Sutherland HDL, Inc. *** ALL RIGHTS RESERVED ***
 * www.sutherland-hdl.com
 *
 * Used with permission in the book, "SystemVerilog for Design"
 *  By Stuart Sutherland, Simon Davidmann, and Peter Flake.
 *  Book copyright: 2003, Kluwer Academic Publishers, Norwell, MA, USA
 *  www.wkap.il, ISBN: 0-4020-7530-8
 *
 * Revision History:
 *   1.00 15 Dec 2003 -- original code, as included in book
 *   1.01 10 Jul 2004 -- cleaned up comments, added expected results
 *                       to output messages
 *
 * Caveat: Expected results displayed for this code example are based
 * on an interpretation of the SystemVerilog 3.1 standard by the code
 * author or authors.  At the time of writing, official SystemVerilog
 * validation suites were not available to validate the example.
 *
 * RIGHT TO USE: This code example, or any portion thereof, may be
 * used and distributed without restriction, provided that this entire
 * comment block is included with the example.
 *
 * DISCLAIMER: THIS CODE EXAMPLE IS PROVIDED "AS IS" WITHOUT WARRANTY
 * OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED
 * TO WARRANTIES OF MERCHANTABILITY, FITNESS OR CORRECTNESS. IN NO
 * EVENT SHALL THE AUTHOR OR AUTHORS BE LIABLE FOR ANY DAMAGES,
 * INCLUDING INCIDENTAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF THE
 * USE OF THIS CODE.
 *********************************************************************/

module test;
  bit   [1:0][15:0] a = { {16'hFFFF},{16'h1111} };  // 32 bit vector
  bit   [3:0][ 7:0] b;  // 32 bit vector
  logic [15:0]      c;  // 16 bit vector
  logic [39:0]      d;  // 40 bit vector

  initial begin
    b = a;  // assign 32-bit array to 32-bit array
    c = a;  // upper 16 bits will be truncated
    d = a;  // upper 8 bits will be zero filled
    $display("\n b = %h (expect ffff1111)", b);
    $display("\n c = %h (expect 1111)", c);
    $display("\n d = %h (expect 00ffff1111)", d);
    $display("");
    $finish;
  end
endmodule