hdpdeps.ref

采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。

V2 37
FL E:/pengfu/EDA/期末报告/DAQ_pengfu/clk_div_10.vhd 2008/12/19.10:32:10 H.38
EN work/CLK_DIV_10 1230789985      FL E:/pengfu/EDA/期末报告/DAQ_pengfu/clk_div_10.vhd \
      PB ieee/STD_LOGIC_1164 1106404628 PB ieee/STD_LOGIC_ARITH 1106404630 \
      PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/CLK_DIV_10/BEHAVIORAL 1230789986 FL E:/pengfu/EDA/期末报告/DAQ_pengfu/clk_div_10.vhd \
      EN work/CLK_DIV_10 1230789985
FL E:/期末报告/DAQ_pengfu/cnt1_0.vhd 2009/01/02.17:51:46 H.38
EN work/CNT1_0 1230889928          FL E:/期末报告/DAQ_pengfu/cnt1_0.vhd \
      PB ieee/STD_LOGIC_1164 1106404628 PB ieee/STD_LOGIC_ARITH 1106404630 \
      PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/CNT1_0/BEHAVIORAL 1230889929 FL E:/期末报告/DAQ_pengfu/cnt1_0.vhd EN work/CNT1_0 1230889928
FL E:/期末报告/DAQ_pengfu/FOUR_0.vhd 2009/01/02.12:55:10 H.38
EN work/FOUR_0 1230891328          FL E:/期末报告/DAQ_pengfu/FOUR_0.vhd \
      PB ieee/STD_LOGIC_1164 1106404628
AR work/FOUR_0/BEHAVIOR 1230891329 FL E:/期末报告/DAQ_pengfu/FOUR_0.vhd EN work/FOUR_0 1230891328
FL e:/FOURTH_1.vhd 2009/01/01.22:30:06 H.38
EN work/FOUR_1 1230820214          FL e:/FOURTH_1.vhd PB ieee/STD_LOGIC_1164 1106404628
AR work/FOUR_1/BEHAVIOR 1230820215 FL e:/FOURTH_1.vhd EN work/FOUR_1 1230820214
FL E:/期末报告/DAQ_pengfu/L_eight_01.vhd 2009/01/02.21:16:00 H.38
EN work/L_EIGHT_01 1230902177      FL E:/期末报告/DAQ_pengfu/L_eight_01.vhd \
      PB ieee/STD_LOGIC_1164 1106404628 PB ieee/STD_LOGIC_ARITH 1106404630 \
      PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/L_EIGHT_01/BEHAVIORAL 1230902178 FL E:/期末报告/DAQ_pengfu/L_eight_01.vhd \
      EN work/L_EIGHT_01 1230902177
FL E:/期末报告/DAQ_pengfu/eight_0S.vhf 2009/01/02.20:53:44 H.38
EN work/EIGHT_0S 0        FL E:/期末报告/DAQ_pengfu/eight_0S.vhf \
      PB ieee/STD_LOGIC_1164 1106404628 PH ieee/NUMERIC_STD 1106404639
AR work/EIGHT_0S/BEHAVIORAL 0 FL E:/期末报告/DAQ_pengfu/eight_0S.vhf \
      EN work/EIGHT_0S 0 CP FOUR_0 CP INV           CP OR2            CP CNT1_0 \
      CP AND2
FL E:/期末报告/DAQ_pengfu/L_1_0.vhd 2009/01/02.20:58:08 H.38
EN work/L_1_0 1230901093           FL E:/期末报告/DAQ_pengfu/L_1_0.vhd \
      PB ieee/STD_LOGIC_1164 1106404628 PB ieee/STD_LOGIC_ARITH 1106404630 \
      PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/L_1_0/BEHAVIORAL 1230901094 FL E:/期末报告/DAQ_pengfu/L_1_0.vhd EN work/L_1_0 1230901093
FL E:/期末报告/DAQ_pengfu/Syn_code_det.vhf 2009/01/02.20:53:42 H.38
EN work/SYN_CODE_DET 0    FL E:/期末报告/DAQ_pengfu/Syn_code_det.vhf \
      PB ieee/STD_LOGIC_1164 1106404628 PH ieee/NUMERIC_STD 1106404639
AR work/SYN_CODE_DET/BEHAVIORAL 0 FL E:/期末报告/DAQ_pengfu/Syn_code_det.vhf \
      EN work/SYN_CODE_DET 0 CP EIGHT_0S CP EITHT_1S CP L_EIGHT_01    CP OR2 \
      CP AND2           CP L_1_0
FL E:/期末报告/DAQ_pengfu/eitht_1S.vhf 2009/01/02.20:53:44 H.38
EN work/EITHT_1S 1230818292        FL E:/期末报告/DAQ_pengfu/eitht_1S.vhf \
      PB ieee/STD_LOGIC_1164 1106404628 PH ieee/NUMERIC_STD 1106404639
AR work/EITHT_1S/BEHAVIORAL 1230818293 FL E:/期末报告/DAQ_pengfu/eitht_1S.vhf \
      EN work/EITHT_1S 1230818292 CP CNT1_0 CP OR2           CP INV            CP AND2 \
      CP FOUR_1