hdllib.ref

采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。

AR l_1_0 behavioral E:/期末报告/DAQ_pengfu/L_1_0.vhd sub00/vhpl17 1230901094
EN eitht_1s NULL E:/pengfu/EDA/期末报告/DAQ_pengfu/eitht_1S.vhf sub00/vhpl10 1230818292
EN l_eight_01 NULL E:/期末报告/DAQ_pengfu/L_eight_01.vhd sub00/vhpl14 1230902177
EN fourth_1 NULL e:/FOURTH_1.vhd sub00/vhpl08 1230818288
AR untitled behavior e:/FOURTH_1.vhd sub00/vhpl07 1230819572
EN four_0 NULL /FOUR_1.vhd sub00/vhpl00 1230891328
EN four_1 NULL e:/FOURTH_1.vhd sub00/vhpl12 1230820214
AR l_eight_01 behavioral E:/期末报告/DAQ_pengfu/L_eight_01.vhd sub00/vhpl15 1230902178
EN l_1_0 NULL E:/期末报告/DAQ_pengfu/L_1_0.vhd sub00/vhpl16 1230901093
EN cnt1_0 NULL E:/期末报告/DAQ_pengfu/cnt1_0.vhd sub00/vhpl04 1230889928
EN clk_div_10 NULL E:/pengfu/EDA/期末报告/DAQ_pengfu/clk_div_10.vhd sub00/vhpl02 1230789985
AR cnt1_0 behavioral E:/期末报告/DAQ_pengfu/cnt1_0.vhd sub00/vhpl05 1230889929
AR four_1 behavior e:/FOURTH_1.vhd sub00/vhpl13 1230820215
AR eitht_1s behavioral E:/pengfu/EDA/期末报告/DAQ_pengfu/eitht_1S.vhf sub00/vhpl11 1230818293
AR four_0 behavior /FOUR_1.vhd sub00/vhpl01 1230891329
EN untitled NULL e:/FOURTH_1.vhd sub00/vhpl06 1230819571
AR clk_div_10 behavioral E:/pengfu/EDA/期末报告/DAQ_pengfu/clk_div_10.vhd sub00/vhpl03 1230789986
AR fourth_1 behavior e:/FOURTH_1.vhd sub00/vhpl09 1230818289