hdllib.ref

采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。

AR l_1_0 behavioral E:/期末报告/DAQ_pengfu/L_1_0.vhd sub00/vhpl41 1230901343
EN t_eight_0s NULL E:/期末报告/DAQ_pengfu/T_eight_0S.vhw sub00/vhpl24 1230874393
EN eitht_1s NULL E:/期末报告/DAQ_pengfu/eitht_1S.vhf sub00/vhpl26 1230902446
EN test_daq NULL E:/pengfu/EDA/期末报告/DAQ_pengfu/test_DAQ.vhw sub00/vhpl16 1230810281
EN t_eight_1s NULL E:/期末报告/DAQ_pengfu/T_eight_1S.vhw sub00/vhpl28 1230891584
AR t_l_1_0 testbench_arch E:/期末报告/DAQ_pengfu/T_l_1_0.vhw sub00/vhpl47 1230901659
AR daq_sch behavioral E:/pengfu/EDA/期末报告/DAQ_pengfu/DAQ_Sch.vhf sub00/vhpl15 1230810280
EN l_eight_01 NULL E:/期末报告/DAQ_pengfu/L_eight_01.vhd sub00/vhpl36 1230902196
EN fourth_1 NULL e:/FOURTH_1.vhd sub00/vhpl18 1230818430
AR t_four_1 testbench_arch E:/期末报告/DAQ_pengfu/T_FOUR_1.vhw sub00/vhpl33 1230891222
AR test_f_0 testbench_arch E:/期末报告/DAQ_pengfu/test_f_0.vhw sub00/vhpl09 1230881220
EN four_0 NULL E:/期末报告/DAQ_pengfu/FOUR_0.vhd sub00/vhpl04 1230872198
EN test_cnt NULL E:/期末报告/DAQ_pengfu/test_cnt.vhw sub00/vhpl12 1230889950
EN four_1 NULL E:/期末报告/DAQ_pengfu/FOUR_1.vhd sub00/vhpl30 1230891580
EN t_four_1 NULL E:/期末报告/DAQ_pengfu/T_FOUR_1.vhw sub00/vhpl32 1230891221
AR l_eight_01 behavioral E:/期末报告/DAQ_pengfu/L_eight_01.vhd sub00/vhpl37 1230902197
EN t_f0 NULL G:/pengfu/EDA/DAQ_pengfu/t_f0.vhw sub00/vhpl06 1229657256
EN l_1_0 NULL E:/期末报告/DAQ_pengfu/L_1_0.vhd sub00/vhpl40 1230901342
AR t_l_eight_01 testbench_arch E:/期末报告/DAQ_pengfu/T_L_eight_01.vhw sub00/vhpl39 1230902287
AR eight_0s behavioral E:/期末报告/DAQ_pengfu/eight_0S.vhf sub00/vhpl23 1230901337
EN cnt1_0 NULL E:/期末报告/DAQ_pengfu/cnt1_0.vhd sub00/vhpl10 1230901334
AR t_syn_code_det testbench_arch E:/期末报告/DAQ_pengfu/T_syn_code_det.vhw sub00/vhpl45 1230902565
EN clk_div_10 NULL E:/期末报告/DAQ_pengfu/clk_div_10.vhd sub00/vhpl00 1230897520
AR cnt1_0 behavioral E:/期末报告/DAQ_pengfu/cnt1_0.vhd sub00/vhpl11 1230901335
AR four_1 behavior E:/期末报告/DAQ_pengfu/FOUR_1.vhd sub00/vhpl31 1230891581
AR eitht_1s behavioral E:/期末报告/DAQ_pengfu/eitht_1S.vhf sub00/vhpl27 1230902447
AR test_four_1 testbench_arch E:/pengfu/EDA/期末报告/DAQ_pengfu/TEST_FOUR_1.vhw sub00/vhpl21 1230815458
AR t_f0 testbench_arch G:/pengfu/EDA/DAQ_pengfu/t_f0.vhw sub00/vhpl07 1229657257
EN eight_0s NULL E:/期末报告/DAQ_pengfu/eight_0S.vhf sub00/vhpl22 1230901336
EN t_eitht_0s NULL E:/期末报告/DAQ_pengfu/T_eitht_0S.vhw sub00/vhpl34 1230890379
EN t_l_eight_01 NULL E:/期末报告/DAQ_pengfu/T_L_eight_01.vhw sub00/vhpl38 1230902286
AR test_cnt testbench_arch E:/期末报告/DAQ_pengfu/test_cnt.vhw sub00/vhpl13 1230889951
AR syn_code_det behavioral E:/期末报告/DAQ_pengfu/Syn_code_det.vhf sub00/vhpl43 1230902563
EN test_four_1 NULL E:/pengfu/EDA/期末报告/DAQ_pengfu/TEST_FOUR_1.vhw sub00/vhpl20 1230815457
AR four_0 behavior E:/期末报告/DAQ_pengfu/FOUR_0.vhd sub00/vhpl05 1230872199
AR t_eitht_0s testbench_arch E:/期末报告/DAQ_pengfu/T_eitht_0S.vhw sub00/vhpl35 1230890380
AR t_eight_0s testbench_arch E:/期末报告/DAQ_pengfu/T_eight_0S.vhw sub00/vhpl25 1230874394
EN t_l_1_0 NULL E:/期末报告/DAQ_pengfu/T_l_1_0.vhw sub00/vhpl46 1230901658
EN syn_code_det NULL E:/期末报告/DAQ_pengfu/Syn_code_det.vhf sub00/vhpl42 1230902562
EN t_syn_code_det NULL E:/期末报告/DAQ_pengfu/T_syn_code_det.vhw sub00/vhpl44 1230902564
AR t_eight_1s testbench_arch E:/期末报告/DAQ_pengfu/T_eight_1S.vhw sub00/vhpl29 1230891585
EN t_clk_div_10 NULL E:/期末报告/DAQ_pengfu/t_clk_div_10.vhw sub00/vhpl02 1230897522
AR test_daq testbench_arch E:/pengfu/EDA/期末报告/DAQ_pengfu/test_DAQ.vhw sub00/vhpl17 1230810282
AR t_clk_div_10 testbench_arch E:/期末报告/DAQ_pengfu/t_clk_div_10.vhw sub00/vhpl03 1230897523
EN daq_sch NULL E:/pengfu/EDA/期末报告/DAQ_pengfu/DAQ_Sch.vhf sub00/vhpl14 1230810279
EN test_f_0 NULL E:/期末报告/DAQ_pengfu/test_f_0.vhw sub00/vhpl08 1230881219
AR clk_div_10 behavioral E:/期末报告/DAQ_pengfu/clk_div_10.vhd sub00/vhpl01 1230897521
AR fourth_1 behavior e:/FOURTH_1.vhd sub00/vhpl19 1230818431