state_control.vhd

VHDL----语言仿真闹钟设计

--------控制电路设计（采用状态机实现）-------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------
entity state_control is
port(clk,time,alarm,reset,keydown:in std_logic;
--	dtime:out std_logic_vector(2 downto 0); 
	show_alarm,show_newtime,load_new_time,load_new_alarm:out std_logic);
end entity state_control;
---------------------------------
architecture one of state_control is
type states is (st0,st1,st2,st3,st4);
signal current_state,next_state:states;
signal current_time,delay_time:std_logic_vector(2 downto 0);---用来控制延时---
begin
---时序进程---
reg:process(clk,reset)
begin
	if reset='1' then current_state<=st0;
	elsif clk'event and clk='1' then current_state<=next_state;current_time<=delay_time;
	end if;
end process reg;
---组合进程---
com:process(current_state,current_time,keydown,alarm,time)
begin
	case current_state is
	when st0 =>show_alarm<='0';show_newtime<='0';load_new_time<='0';load_new_alarm<='0';
				if keydown='1' then next_state<=st1;delay_time<="000";--转到状态1，并将延时时间设为0。
			--	else next_state<=st0;
			--	end if;
				elsif alarm='1' then next_state<=st4;delay_time<="000";
				else next_state<=st0;
				end if;
	when st1 =>
				show_alarm<='0';show_newtime<='1';load_new_time<='0';load_new_alarm<='0';
				if current_time="100" then next_state<=st0;
				elsif keydown='1' then next_state<=st1;delay_time<="000";
				elsif alarm='1' then next_state<=st2;
				elsif time='1' then next_state<=st3;
				else next_state<=st1;delay_time<=current_time+1;
				end if;
	when st2 =>show_alarm<='0';show_newtime<='0';load_new_time<='0';load_new_alarm<='1';
				if alarm='1' then next_state<=st2;
				else next_state<=st0;
				end if;
	when st3 =>show_alarm<='0';show_newtime<='0';load_new_time<='1';load_new_alarm<='0';
				if time='1' then next_state<=st3;
				else next_state<=st0;
				end if;
	when st4 =>show_alarm<='1';show_newtime<='0';load_new_time<='0';load_new_alarm<='0';
				if current_time="100" then next_state<=st0;
				elsif alarm='1' then next_state<=st4;delay_time<="000";
				else next_state<=st4;delay_time<=current_time+1;
				end if;
	end case;
	
end process com;
--dtime<=current_time;
end architecture one;