light.tan.qmsg

这是一个用VHDL编写的发光二极管走马灯

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 19 10:56:21 2006 " "Info: Processing started: Fri May 19 10:56:21 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off light -c light " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off light -c light" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clo " "Info: Assuming node clo is an undefined clock" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 5 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clo" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clo register a\[2\] register a~0 76.92 MHz 13.0 ns Internal " "Info: Clock clo has Internal fmax of 76.92 MHz between source register a\[2\] and destination register a~0 (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a\[2\] 1 REG LC36 37 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a\[2\]'" {  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { a[2] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns a~0 2 REG LC46 2 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC46; Fanout = 2; REG Node = 'a~0'" {  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "8.000 ns" { a[2] a~0 } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "8.000 ns" { a[2] a~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clo destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clo to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clo 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'" {  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { clo } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns a~0 2 REG LC46 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC46; Fanout = 2; REG Node = 'a~0'" {  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "0.000 ns" { clo a~0 } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a~0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clo source 3.000 ns - Longest register " "Info: - Longest clock path from clock clo to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clo 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'" {  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { clo } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns a\[2\] 2 REG LC36 37 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a\[2\]'" {  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "0.000 ns" { clo a[2] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a[2] } "NODE_NAME" } } }  } 0}  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a~0 } "NODE_NAME" } } } { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } }  } 0}  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "8.000 ns" { a[2] a~0 } "NODE_NAME" } } } { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a~0 } "NODE_NAME" } } } { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "a\[2\] btn2 clo 11.000 ns register " "Info: tsu for register a\[2\] (data pin = btn2, clock pin = clo) is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns btn2 1 PIN PIN_1 36 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 36; PIN Node = 'btn2'" {  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { btn2 } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns a\[2\] 2 REG LC36 37 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a\[2\]'" {  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "7.000 ns" { btn2 a[2] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" {  } {  } 0}  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "10.000 ns" { btn2 a[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clo destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock clo to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clo 1 CLK PIN_83 8 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 8; CLK Node = 'clo'" {  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "" { clo } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns a\[2\] 2 REG LC36 37 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC36; Fanout = 37; REG Node = 'a\[2\]'" {  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "0.000 ns" { clo a[2] } "NODE_NAME" } } } { "D:/YES OR NO/light/light.vhd" "" "" { Text "D:/YES OR NO/light/light.vhd" 42 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a[2] } "NODE_NAME" } } }  } 0}  } { { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "10.000 ns" { btn2 a[2] } "NODE_NAME" } } } { "D:/YES OR NO/light/db/light_cmp.qrpt" "" "" { Report "D:/YES OR NO/light/db/light_cmp.qrpt" Compiler "light" "UNKNOWN" "V1" "D:/YES OR NO/light/db/light.quartus_db" { Floorplan "" "" "3.000 ns" { clo a[2] } "NODE_NAME" } } }  } 0}