dz.vhd

本程序是用VHDL编写

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity dz is 
	port(clk,k:in std_logic;					
		   h,l:out std_logic_vector(7 downto 0);
		   LED:out std_logic_vector(2 downto 0));		
end dz;

architecture dz of dz is
	component fd		            --fangdou
		port(clk,key:in std_logic;
		cpo:out std_logic);
	end component;
	component div		            --fenpin
		port(clk:in std_logic;
			 y:out std_logic);
	end component;
	component ql		            --manpin
		port(clk:in std_logic;
			  ho,lo:out std_logic_vector(7 downto 0));
	end component;
	component sm		            --saomiao
		port(clk:in std_logic;
			  ho,lo:out std_logic_vector(7 downto 0));
	end component;
	component xs		            --xianshi
		port(clk:in std_logic;
			  ho,lo:out std_logic_vector(7 downto 0));
	end component;
	component gd		            --gundong
		port(clk:in std_logic;
 			  ho,lo:out std_logic_vector(7 downto 0));
	end component;

signal state:std_logic_vector(1 downto 0):="00";		
signal h0,l0,h1,l1,h2,l2,h3,l3:std_logic_vector(7 downto 0);	
signal tempclk:std_logic;		
signal kz:std_logic;	
		
begin
d1:div port map(clk,tempclk);		
f1:fd port map(tempclk,k,kz);			
m1:ql port map(tempclk,h0,l0);	
m2:sm port map(tempclk,h1,l1);	
m3:xs port map(tempclk,h2,l2);	
m4:gd port map(tempclk,h3,l3);	
process(kz)
	begin
		if(kz'event and kz='1')then		
			case state is		
				when "00"=>			
					state<="01";
				when "01"=>
					state<="10";
				when "10"=>
					state<="11";
				when others =>
					state<="00";
			end case;
		end if;
		case state is
			when "01"=> h<=h1;l<=l1;LED<="100";	
			when "10"=> h<=h2;l<=l2;LED<="010";	
			when "11"=> h<=h3;l<=l3;LED<="001";	
			when others=> h<=h0;l<=l0;LED<="111";	
		end case;
end process;
end;