ql.vhd

本程序是用VHDL编写

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity ql is		
	port(clk:in std_logic;		
		  --st:in std_logic_vector(1 downto 0);	
		  ho:out std_logic_vector(7 downto 0);		
		  lo:out std_logic_vector(7 downto 0));		
end ql;

architecture ql of ql is

signal cout:std_logic_vector(2 downto 0);

begin
p1:process(clk)
	begin
		if(clk'event and clk='1')then	
           cout<=cout+1;
        end if;
end process;
p2:process(clk)
     begin
        if(clk'event and clk='1')then	
           case cout is
                    when"000"=>ho<="10000000";lo<="00000000";
					when"001"=>ho<="01000000";lo<="00000000";
					when"010"=>ho<="00100000";lo<="00000000";
					when"011"=>ho<="00010000";lo<="00000000";
					when"100"=>ho<="00001000";lo<="00000000";
					when"101"=>ho<="00000100";lo<="00000000";
					when"110"=>ho<="00000010";lo<="00000000";
					when"111"=>ho<="00000001";lo<="00000000";
					when others=>ho<="00000000";lo<="00000000";
				end case;
		end if;	
end process;
end ;