fd.vhd

本程序是用VHDL编写

library ieee;
use ieee.std_logic_1164.all;

entity fd is			
	port(clk,key:in std_logic;		
			cpo:out std_logic);		
end fd;

architecture jg of fd is
	signal cp:std_logic;			       
	signal jsq:integer range 0 to 10;		
begin

process(clk)
	begin
		if(clk'event and clk='1')then		
			if key='1'then			
				if jsq=10 then	 --keep jsq	
					jsq<=jsq;
				else
					jsq<=jsq+1;		
				end if;
			else				
				jsq<=0;			
			end if;
			if jsq=9 then		
				cp<='1';        
			else
				cp<='0';
			end if;
		end if;
		cpo<=cp;		
end process;
end;