rptr_empty.v

精通verilog_hdl语言编程实例程序代码

// 读指针与"空"逻辑
module rptr_empty (rempty, rptr, aempty_n, rreq, rclk, rrst_n);
	parameter ADDR_WIDTH = 4;
	output rempty;
	output [ADDR_WIDTH-1:0] rptr;
	input aempty_n;
	input rreq, rclk, rrst_n;
	reg [ADDR_WIDTH-1:0] rptr, rbin;
	reg rempty, rempty2;
	wire [ADDR_WIDTH-1:0] rgnext, rbnext;
	
	// 寄存器输出Gray码读地址指针
	always @(posedge rclk or negedge rrst_n)
		if (!rrst_n) begin
			rbin <= 0;
			rptr <= 0;
		end
		else begin
			rbin <= rbnext;
			rptr <= rgnext;
		end

	// Gray码计数逻辑
	assign rbnext = !rempty ? rbin + rreq : rbin;
	assign rgnext = (rbnext>>1) ^ rbnext; // 二进制到Gray码转换

	always @(posedge rclk or negedge aempty_n)
		if (!aempty_n) 
			{rempty,rempty2} <= 2'b11;
		else 
			{rempty,rempty2} <= {rempty2,~aempty_n};
Endmodule