fir_gen.v

精通verilog_hdl语言编程实例程序代码

module fir_gen(clk,Load_x,x_in,c_in,y_out);

parameter W1=9,W2=18,W3=19,W4=11,L=4,Mpipe=3;
input clk,Load_x;
input [W1-1:0] x_in,c_in;
output [W3-1:0] y_out;

reg [W1-1:0] x;
wire [W3-1:0] y;

reg [W1-1:0] c0,c1,c2,c3;
wire [W2-1:0] p0,p1,p2,p3;
reg [w3-1:0] a0,a1,a2,a3;

wire [W2-1:0] sum;
wire clken,aclr;

assign sum=0;assign aclr=0;assign clken=0;

always @(posedge clk)
  begin:Load
   if(!Load_x) begin
      c3<=c_in;
      c2<=c3;
      c1<=c2;
      c0<=c1;
      end
    else begin
         x=x_in;
         end
  end

always @(posedge clk)
  begin:SOP
  a0<={p0[W2-1],p0}+a1;
  a1<={p1[W2-1],p1}+a2;
  a2<={p2[W2-1],p2}+a3;
  a3<={p3[W2-1],p3};
  end
assign y=a0;

lpm_mult mul_0(.clock(clk),.dataa(x),.datab(c0),.result(p0));
defparam mul_0.lpm_widtha=W1;
defparam mul_0.lpm_widthb=W1;
defparam mul_0.lpm_widthp=W2;
defparam mul_0.lpm_widths=W2;
defparam mul_0.lpm_pipeline=Mpipe;
defparam mul_0.lpm_representation="SIGNED";


lpm_mult mul_1(.clock(clk),.dataa(x),.datab(c1),.result(p1));
defparam mul_1.lpm_widtha=W1;
defparam mul_1.lpm_widthb=W1;
defparam mul_1.lpm_widthp=W2;
defparam mul_1.lpm_widths=W2;
defparam mul_1.lpm_pipeline=Mpipe;
defparam mul_1.lpm_representation="SIGNED";


lpm_mult mul_2(.clock(clk),.dataa(x),.datab(c2),.result(p2));
defparam mul_2.lpm_widtha=W1;
defparam mul_2.lpm_widthb=W1;
defparam mul_2.lpm_widthp=W2;
defparam mul_2.lpm_widths=W2;
defparam mul_2.lpm_pipeline=Mpipe;
defparam mul_2.lpm_representation="SIGNED";

lpm_mult mul_3(.clock(clk),.dataa(x),.datab(c3),.result(p3));
defparam mul_3.lpm_widtha=W1;
defparam mul_3.lpm_widthb=W1;
defparam mul_3.lpm_widthp=W2;
defparam mul_3.lpm_widths=W2;
defparam mul_3.lpm_pipeline=Mpipe;
defparam mul_3.lpm_representation="SIGNED";

assign y_out=y[W3-1:W3-W4];
endmodule