rs_decoder.v

精通verilog_hdl语言编程实例程序代码

module rs_decoder(clk, rst, sync, Din, Dout);
	parameter	 t = 8,		// t--The total number of errors that can be corrected
				 N = 204,	// N--Codeword length
				 m = 8;		// m--Extension of GF(2)
				
	input 		   clk, rst, sync;
	input  [m-1:0] Din;
	output [m-1:0] Dout;

	
	wire 		 Err_Indicator;
	wire [m-1:0] ErrorVal;
	reg  [m-1:0] Dout;
	always @(posedge clk)begin
		if(Err_Indicator) Dout <= shift_out ^ ErrorVal;
		else			  Dout <= shift_out;
	end 

	wire  [m-1:0] sc_s_out;
	wire 		  sc_done;
	SCalculate inst_sc(.clk(clk), 
					.init(sync), 
					.sc_done(sc_done), 
					.r(Din), 
					.s_out(sc_s_out));
					
	wire [m-1:0] kes_s_out, Lmd0, Lmd1, Lmd2, Lmd3, Lmd4, Lmd5, Lmd6, Lmd7, Lmd8, L;
	wire		 kes_done;
	BM_KES inst_kes(.S(sc_s_out), 
					.clk(clk), 
					.kes_init(sc_done), 
					.kes_done(kes_done), 
					.Lmd0(Lmd0), .Lmd1(Lmd1), .Lmd2(Lmd2), 
					.Lmd3(Lmd3), .Lmd4(Lmd4), .Lmd5(Lmd5), 
					.Lmd6(Lmd6), .Lmd7(Lmd7), .Lmd8(Lmd8),
					.L(L), 
					.s_out(kes_s_out));


	error_valuator 	inst_eval (.clk(clk), 
						.init(kes_done), 
						.s(kes_s_out), 
						.Lmd0(Lmd0), .Lmd1(Lmd1), .Lmd2(Lmd2), 
						.Lmd3(Lmd3), .Lmd4(Lmd4), .Lmd5(Lmd5),
						.Lmd6(Lmd6), .Lmd7(Lmd7), .Lmd8(Lmd8),
						.ErrorValue(ErrorVal));

	CheinSearch 	inst_ChS(.clk(clk), 
						.init(kes_done), 
						.Lmd0(Lmd0), .Lmd1(Lmd1), .Lmd2(Lmd2), 
						.Lmd3(Lmd3), .Lmd4(Lmd4), .Lmd5(Lmd5),
						.Lmd6(Lmd6), .Lmd7(Lmd7), .Lmd8(Lmd8),
						.Err_Indicator(Err_Indicator));
						
	wire  [m-1:0] shift_out;
	altshift_taps	inst_SR(
						.clock (clk),
						.shiftin (Din),
						.taps (),
						.shiftout (shift_out)
						// synopsys translate_off
						,
						.clken ()
						// synopsys translate_on
						);
	defparam
		inst_SR.width = 8,
		inst_SR.number_of_taps = 1,
		inst_SR.tap_distance = 243,
		inst_SR.lpm_type = "altshift_taps";
		
endmodule