top_pci32.map.qmsg

Altera的MAXIICPLD模拟PCI接口的Verilog代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 06 12:55:16 2005 " "Info: Processing started: Wed Apr 06 12:55:16 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off top_pci32 -c top_pci32 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off top_pci32 -c top_pci32" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "local/top_local.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file local/top_local.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_local " "Info: Found entity 1: top_local" {  } { { "local/top_local.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/local/top_local.v" 41 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "local/lcd_cntrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file local/lcd_cntrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_cntrl " "Info: Found entity 1: lcd_cntrl" {  } { { "local/lcd_cntrl.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/local/lcd_cntrl.v" 26 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "local/mem_cntrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file local/mem_cntrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 mem_cntrl " "Info: Found entity 1: mem_cntrl" {  } { { "local/mem_cntrl.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/local/mem_cntrl.v" 34 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "local/perip.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file local/perip.v" { { "Info" "ISGN_ENTITY_NAME" "1 perip " "Info: Found entity 1: perip" {  } { { "local/perip.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/local/perip.v" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "local/temp_cntrl.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file local/temp_cntrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 temp_cntrl " "Info: Found entity 1: temp_cntrl" {  } { { "local/temp_cntrl.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/local/temp_cntrl.v" 30 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "lt_rdyn top_pci32.v(116) " "Warning: Verilog HDL net warning at top_pci32.v(116): created undeclared net \"lt_rdyn\"" {  } { { "top_pci32.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/top_pci32.v" 116 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "lt_abortn top_pci32.v(117) " "Warning: Verilog HDL net warning at top_pci32.v(117): created undeclared net \"lt_abortn\"" {  } { { "top_pci32.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/top_pci32.v" 117 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "lt_discn top_pci32.v(118) " "Warning: Verilog HDL net warning at top_pci32.v(118): created undeclared net \"lt_discn\"" {  } { { "top_pci32.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/top_pci32.v" 118 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "lirqn top_pci32.v(119) " "Warning: Verilog HDL net warning at top_pci32.v(119): created undeclared net \"lirqn\"" {  } { { "top_pci32.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/top_pci32.v" 119 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "sram_ce2 top_pci32.v(123) " "Warning: Verilog HDL net warning at top_pci32.v(123): created undeclared net \"sram_ce2\"" {  } { { "top_pci32.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/top_pci32.v" 123 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "lt_framen top_pci32.v(142) " "Warning: Verilog HDL net warning at top_pci32.v(142): created undeclared net \"lt_framen\"" {  } { { "top_pci32.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/top_pci32.v" 142 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "lt_ackn top_pci32.v(143) " "Warning: Verilog HDL net warning at top_pci32.v(143): created undeclared net \"lt_ackn\"" {  } { { "top_pci32.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/top_pci32.v" 143 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "lt_dxfrn top_pci32.v(144) " "Warning: Verilog HDL net warning at top_pci32.v(144): created undeclared net \"lt_dxfrn\"" {  } { { "top_pci32.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/top_pci32.v" 144 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_pci32.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file top_pci32.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_pci32 " "Info: Found entity 1: top_pci32" {  } { { "top_pci32.v" "" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/top_pci32.v" 33 -1 0 } }  } 0}  } {  } 0}
{ "Error" "ESGN_ENTITY_IS_MISSING" "core t32 " "Error: Node instance \"core\" instantiates undefined entity \"t32\"" {  } { { "top_pci32.v" "core" { Text "E:/MAXIIDevelopmentKit-v1.0.0/Examples/HW/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/rtl/top_pci32.v" 184 -1 0 } }  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  8 s " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 8 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Wed Apr 06 12:55:19 2005 " "Error: Processing ended: Wed Apr 06 12:55:19 2005" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:05 " "Error: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}