📄 t32.html
字号:
<HTML><HEAD><style>
A.h:hover { color: "#FF0000"; }A.menu:link { text-decoration: none}A.menu:visited{ text-decoration: none}A.menu:hover {color: #EE9B06;}A.submenu:link { text-decoration: none;}A.submenu:visited { text-decoration: none}A.submenu:hover {color: #EE9B06;}div.category { border-bottom: 5px, solid, black; }br.submenu { line-height: 1em;}br.submenu { line-height: 7px;}BODY, H1, H2, H3, H4, TD, TH, UL, OL, LI, P, DD, DT, DL, INPUT, SELECT, SPAN { font-family : SansSerif, Verdana, Helvetica, Arial, San-sarif; }BODY { background-color : #e0e0e0; }TD, UL, OL, LI, P, DD, DT, DL, SPAN { font-size: 11pt; color : black; }BLOCKQUOTE { font-size: 10pt; color : #000099; }TH { font-size : 11pt; font-weight : bold; font-style : normal; color : black; }H1 { font-size : 18pt; color : black; }H2 { font-size : 14pt; color : black; }H3 { font-size : 12pt; color : black; }H4 { font-size : 11pt; font-weight : bold; color : black; }
</style></HEAD><BODY align=left style='background-color: #ffffff;'><DIV align=left><TABLE width=95% border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - PCI Compiler v3.2.0</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width=60%><TR><TD><B>Entity Name</B></TD><TD>pci_t32</TD></TR><TR><TD><B>Variation Name</B></TD><TD>t32</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>C:\Designs\maxii_ref\rtl\core</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>IP Toolbench is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width=100%><TR align=left><TH align=left align=top width=25%><B>File</B></TH><TH align=left><B>Description</B></TH></TR><TR><TD>t32.v</TD><TD>A MegaCore<small><sup>®</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>t32_inst.v</TD><TD>Verilog HDL sample instantiation file</TD></TR><TR><TD>t32.cmp</TD><TD>A VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>t32.inc</TD><TD>An AHDL include declaration file for the MegaCore function variation. Include this file with any AHDL architecture that instantiates the MegaCore function.</TD></TR><TR><TD>t32_bb.v</TD><TD>Verilog HDL black-box file for the MegaCore function variation. Use this file when using a third-party EDA tool to synthesize your design.</TD></TR><TR><TD>t32.bsf</TD><TD>Quartus<small><sup>®</sup></small> II symbol file for the MegaCore function variation. You can use this file in the Quartus II block diagram editor.</TD></TR><TR><TD>t32.vo</TD><TD>Verilog HDL IP functional simulation model.</TD></TR><TR><TD>t32.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Parameters</h2><TABLE border=1 cellpadding=2 cellspacing=0 width=75%><TR align=left><TH align=left><B>Name</B></TH><TH align=left><B>Value</B></TH></TR><TR ><TD>CLASS_CODE</TD><TD>FF0000</TD></TR><TR ><TD>DEVICE_ID</TD><TD>0008</TD></TR><TR ><TD>REVISION_ID</TD><TD>01</TD></TR><TR ><TD>SUBSYSTEM_ID</TD><TD>D000</TD></TR><TR ><TD>SUBSYSTEM_VENDOR_ID</TD><TD>0000</TD></TR><TR ><TD>TARGET_DEVICE</TD><TD>NEW</TD></TR><TR ><TD>VENDOR_ID</TD><TD>1172</TD></TR><TR ><TD>MIN_GRANT</TD><TD>00</TD></TR><TR ><TD>MAX_LATENCY</TD><TD>00</TD></TR><TR ><TD>CAP_PTR</TD><TD>40</TD></TR><TR ><TD>CIS_PTR</TD><TD>00000001</TD></TR><TR ><TD>BAR0</TD><TD>FFFE0000</TD></TR><TR ><TD>BAR1</TD><TD>FFFFFFF1</TD></TR><TR ><TD>BAR2</TD><TD>FFF00000</TD></TR><TR ><TD>BAR3</TD><TD>FFF00000</TD></TR><TR ><TD>BAR4</TD><TD>FFF00000</TD></TR><TR ><TD>BAR5</TD><TD>FFF00000</TD></TR><TR ><TD>NUMBER_OF_BARS</TD><TD>2</TD></TR><TR ><TD>HARDWIRE_BAR0</TD><TD>00000000</TD></TR><TR ><TD>HARDWIRE_BAR1</TD><TD>00000000</TD></TR><TR ><TD>HARDWIRE_BAR2</TD><TD>00000000</TD></TR><TR ><TD>HARDWIRE_BAR3</TD><TD>00000000</TD></TR><TR ><TD>HARDWIRE_BAR4</TD><TD>00000000</TD></TR><TR ><TD>HARDWIRE_BAR5</TD><TD>00000000</TD></TR><TR ><TD>HARDWIRE_EXP_ROM</TD><TD>00000001</TD></TR><TR ><TD>EXP_ROM_BAR</TD><TD>FFF00000</TD></TR><TR ><TD>PCI_66MHZ_CAPABLE</TD><TD>NO</TD></TR><TR ><TD>INTERRUPT_PIN_REG</TD><TD>1</TD></TR><TR ><TD>ENABLE_BITS</TD><TD>00000000</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width=75%><TR align=left><TH align=left><B>Name</B></TH><TH align=left><B>Direction</B></TH><TH align=left><B>Width</B></TH></TR><TR><TD>clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>rstn</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>idsel</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>l_adi</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>lt_rdyn</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>lt_abortn</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>lt_discn</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>lirqn</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>cben</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>intan</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>serrn</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>l_adro</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>l_dato</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>l_beno</TD><TD>OUTPUT</TD><TD>4</TD></TR><TR><TD>l_cmdo</TD><TD>OUTPUT</TD><TD>4</TD></TR><TR><TD>lt_framen</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>lt_ackn</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>lt_dxfrn</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>lt_tsr</TD><TD>OUTPUT</TD><TD>12</TD></TR><TR><TD>cmd_reg</TD><TD>OUTPUT</TD><TD>7</TD></TR><TR><TD>stat_reg</TD><TD>OUTPUT</TD><TD>7</TD></TR><TR><TD>ad</TD><TD>BIDIR</TD><TD>32</TD></TR><TR><TD>par</TD><TD>BIDIR</TD><TD>1</TD></TR><TR><TD>perrn</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>framen_in</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>irdyn_in</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>devseln_out</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>trdyn_out</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>stopn_out</TD><TD>OUTPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -