mem_interface_top_rd_wr_addr_fifo_0.txt

利用fpga读写ddr的源代码 实测可以使用

///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : $Name: mig_v1_7 $
//  \   \        Application        : MIG
//  /   /        Filename           : mem_interface_top_rd_wr_addr_fifo_0.v
// /___/   /\    Date Last Modified : $Date: 2007/02/15 12:06:16 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
//
// Device      : Virtex-4
// Design Name : DDR SDRAM
// Description: Instantiates the block RAM based FIFO to store the user address
//              and the command information.
///////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

`include "../rtl/mem_interface_top_parameters_0.v"

module mem_interface_top_rd_wr_addr_fifo_0
  (
   input         clk0,
   input         clk90,
   input         rst,
   input[35:0]   app_af_addr,
   input         app_af_WrEn,
   input         ctrl_af_RdEn,

   output[35:0]  af_addr,
   output        af_Empty,
   output reg    af_Almost_Full
   );


   reg [35:0] compare_value_r;
   reg [35:0] app_af_addr_r;
   reg [35:0] fifo_input_addr_r;
   reg 	      af_en_r;
   reg 	      af_en_2r;
   wire       compare_result;
   wire [35:0] fifo_input_write_addr;
   wire [35:0] fifo_output_write_addr;
   wire        clk270;
   wire        af_al_full_0;

   reg 	       af_en_2r_270;
   reg [35:0]  fifo_input_270;
   reg 	       af_al_full_180;
   reg 	       af_al_full_90;
   reg 	       rst_r;

   always @( posedge clk0 )
     rst_r <= rst;

   // [31:29]  -- command to controller
   // [28]     -- conflict bit
   // [27:0]   --- address

   assign fifo_input_write_addr[35:0] = {compare_result, app_af_addr_r[34:0]};
   assign af_addr[35:0] = fifo_output_write_addr;
   assign compare_result = (compare_value_r[`no_of_cs+`bank_address+`row_address+
					    `col_ap_width- 1:`col_ap_width]
			    == fifo_input_write_addr[`no_of_cs + `bank_address +
						     `row_address+`col_ap_width-1:
						     `col_ap_width]) ? 1'b0: 1'b1;
   assign clk270 = ~clk90;


   always @(posedge clk0) begin
      if(rst_r) begin
	 compare_value_r         <= 36'h0000;
	 app_af_addr_r[35:0]     <= 36'd0;
	 fifo_input_addr_r[35:0] <= 36'd0;
	 af_en_r                 <= 1'b0;
	 af_en_2r                <= 1'b0;
      end
      else begin
	 if(af_en_r)
           compare_value_r      <= fifo_input_write_addr;
	 app_af_addr_r[35:0]    <= app_af_addr[35:0];
	 fifo_input_addr_r[35:0]<= fifo_input_write_addr[35:0];
	 af_en_r                <= app_af_WrEn;
	 af_en_2r               <= af_en_r;
      end
   end

   // A fix for FIFO16 similar to answer record #22462

   always @(posedge clk270) begin
      af_en_2r_270    <= af_en_2r;
      fifo_input_270  <= fifo_input_addr_r;
   end

   // 3 Filp-flops logic is implemented at output to avoid the timimg errors

   always @(negedge clk0) begin
      af_al_full_180 <= af_al_full_0;
   end

   always @(posedge clk90) begin
      af_al_full_90 <= af_al_full_180;
   end

   always @(posedge clk0) begin
      af_Almost_Full <= af_al_full_90;
   end

   // Read/Write Address FIFO

   defparam af_fifo16.ALMOST_EMPTY_OFFSET = 12'h007;
   defparam af_fifo16.ALMOST_FULL_OFFSET = 12'h00F;
   defparam af_fifo16.DATA_WIDTH = 36;
   defparam af_fifo16.FIRST_WORD_FALL_THROUGH = "TRUE";


   FIFO16  af_fifo16
     (
      .ALMOSTEMPTY (),
      .ALMOSTFULL  (af_al_full_0),
      .DO          (fifo_output_write_addr[31:0]),
      .DOP         (fifo_output_write_addr[35:32]),
      .EMPTY       (af_Empty),
      .FULL        (),
      .RDCOUNT     (),
      .RDERR       (),
      .WRCOUNT     (),
      .WRERR       (),
      .DI          (fifo_input_270[31:0]),
      .DIP         (fifo_input_270[35:32]),
      .RDCLK       (clk0),
      .RDEN        (ctrl_af_RdEn),
      .RST         (rst_r),
      .WRCLK       (clk270),
      .WREN        (af_en_2r_270)
      );

endmodule