mem_interface_top_ddr_controller_0.txt

利用fpga读写ddr的源代码 实测可以使用

        ext_mode_reg         <=  af_addr [`row_address-1:0];
   end

   //to initialize memory
   always @ (posedge clk_0) begin
      if ((rst_r)|| (init_state == INIT_DEEP_MEMORY_ST)) begin
         init_memory <= 1'b1;
      end
      else if (init_count_cp == 4'hA) begin
         init_memory <= 1'b0;
      end
           else begin
              init_memory <= init_memory;
           end
   end

   // mrd count
   always @ (posedge clk_0) begin
      if (rst_r)
         mrd_count <= 1'b0;
      else if (state == LOAD_MODE_REG_ST)
        mrd_count <= `mrd_count_value;
      else if (mrd_count != 1'b0)
        mrd_count <= 1'b0;
      else
        mrd_count <= 1'b0;
   end

   // rp count
   always @ (posedge clk_0) begin
      if (rst_r)
        rp_count[2:0] <= 3'b000;
      else if (state == PRECHARGE)
        rp_count[2:0] <= `rp_count_value;
      else if (rp_count[2:0] != 3'b000)
        rp_count[2:0] <= rp_count[2:0] - 1;
      else
        rp_count[2:0] <= 3'b000;
   end

   // rfc count
   always @ ( posedge clk_0) begin
      if (rst_r)
        rfc_count[5:0] <= 6'b000000;
      else if (state == AUTO_REFRESH)
        rfc_count[5:0] <= `rfc_count_value;
      else if (rfc_count[5:0] != 6'b000000)
        rfc_count[5:0] <= rfc_count[5:0] - 1;
      else
        rfc_count[5:0] <= 6'b00_0000;
   end

   // rcd count - 20ns
   always @ ( posedge clk_0) begin
      if (rst_r)
        rcd_count[2:0] <= 3'b000;
      else if (state == ACTIVE)
        rcd_count[2:0] <= `rcd_count_value;
      else if (rcd_count[2:0] != 3'b000)
        rcd_count[2:0] <= rcd_count[2:0] - 1;
      else
        rcd_count[2:0] <=  3'b000;
   end


   // ras count - active to precharge
   always @ ( posedge clk_0) begin
      if (rst_r)
         ras_count[3:0] <= 4'b0000;
      else if (state == ACTIVE)
         ras_count[3:0] <= `ras_count_value;
      else if (ras_count[3:1] == 3'b000) begin
         if (ras_count[0] != 1'b0)
           ras_count[0] <= 1'b0;
      end
      else  begin
         ras_count[3:0] <= ras_count[3:0] - 1;
      end
   end // always @ ( posedge clk_0)

   //AL+BL/2+TRTP-2
   // rtp count - read to precharge
   always @ ( posedge clk_0) begin
      if (rst_r)
        rtp_count[3:0] <= 4'b0000;
      else if (read_state)
        rtp_count[3:0] <= (`trtp_count_value ) ;
      else if (rtp_count[3:1] == 3'b000) begin
       if (rtp_count[0] != 1'b0)
         rtp_count[0] <= 1'b0;
      end
      else begin
       rtp_count[3:0] <= rtp_count[3:0] - 1;
      end
   end // always @ ( posedge clk_0)

   // WL+BL/2+TWR
   // wtp count - write to precharge
   always @ ( posedge clk_0) begin
      if (rst_r)
       wtp_count[3:0] <= 4'b0000;
      else if (write_state)
       wtp_count[3:0] <= (`twr_count_value)  ;
      else if (wtp_count[3:1] == 3'b000) begin
       if (wtp_count[0] != 1'b0)
              wtp_count[0] <= 1'b0;
      end
      else
       wtp_count[3:0] <= wtp_count[3:0] - 1;
   end // always @ ( posedge clk_0)

   // write to read counter
   always @ (posedge clk_0) begin
      if (rst_r)
        wr_to_rd_count[3:0] <= 4'b0000;
      else if (write_state)
        wr_to_rd_count[3:0] <= (`twtr_count_value );
      else if (wr_to_rd_count[3:0] != 4'b0000)
         wr_to_rd_count[3:0] <= wr_to_rd_count[3:0] - 1;
      else
        wr_to_rd_count[3:0] <= 4'b0000;
   end

   // read to write counter
   always @ (posedge clk_0) begin
      if (rst_r)
        rd_to_wr_count[3:0] <= 4'b0000;
      else if (read_state)
        rd_to_wr_count[3:0] <= ( `registered + burst_cnt + load_mode_reg[6] +
                                 load_mode_reg[4]);
      else if (rd_to_wr_count[3:0] != 4'b0000)
        rd_to_wr_count[3:0] <= rd_to_wr_count[3:0] - 1;
      else
        rd_to_wr_count[3:0] <= 4'b0000;
   end

   // auto refresh interval counter in clk_0 domain
   always @ (posedge clk_0) begin
      if (rst_r)
        refi_count <= 8'h00;
      else if (refi_count == `max_ref_cnt )
        refi_count <= 8'h00;
      else
        refi_count <= refi_count + 1;
   end

   assign ref_flag = ((refi_count == `max_ref_cnt) && (done_200us == 1'b1) )
                                ? 1'b1 : 1'b0;

   //200us counter for cke
   always @ (posedge clk_0) begin
      if (rst_r )
        cke_200us_cnt <= 5'b11011;
      else if (refi_count[`max_ref_width-1 : 0] ==  `max_ref_cnt)
        cke_200us_cnt  <=  cke_200us_cnt - 1;
           else
             cke_200us_cnt  <= cke_200us_cnt;
   end

   // refresh detect
   always @ (posedge clk_0) begin
      if (rst_r) begin
         ref_flag_0   <= 1'b0;
         ref_flag_0_r <= 1'b0;
         done_200us <= 1'b0;
      end
      else begin
         ref_flag_0   <= ref_flag;
         ref_flag_0_r <= ref_flag_0;
      `ifdef simulation
         done_200us <= 1'b1;
      `else
         if (done_200us == 1'b0)
           done_200us <= (cke_200us_cnt == 5'b00000);
      `endif
      end
   end // always @ (posedge clk_0)

   //refresh flag detect
   //auto_ref high indicates auto_refresh requirement
   //auto_ref is held high until auto refresh command is issued.
   always @(posedge clk_0) begin
      if (rst_r)
        auto_ref <= 1'b0;
      else if (ref_flag_0 == 1'b1 && ref_flag_0_r == 1'b0)
        auto_ref <= 1'b1;
      else if ((state == AUTO_REFRESH) || (init_state == INIT_AUTO_REFRESH))
        auto_ref <= 1'b0;
      else
        auto_ref <= auto_ref;
   end

   // 200 clocks counter - count value : C8
   // required for initialization
   always @ (posedge clk_0) begin
      if (rst_r)
        count_200_cycle[7:0] <= 8'h00;
      else if (init_state == INIT_INITCOUNT_200)
        count_200_cycle[7:0] <= 8'hC8;
      else if (count_200_cycle[7:0] != 8'h00)
        count_200_cycle[7:0] <= count_200_cycle[7:0] - 1;
      else
        count_200_cycle[7:0] <= 8'h00;
   end

   always @ (posedge clk_0) begin
      if (rst_r)
         count_200cycle_done_r<= 1'b0;
      else if (init_memory && (count_200_cycle == 8'h00))
        count_200cycle_done_r<= 1'b1;
      else
        count_200cycle_done_r<= 1'b0;
   end

   always @ (posedge clk_0) begin
      if (rst_r)
         init_done_int <= 1'b0;
      else if ((`Phy_Mode == 1'b1) && (comp_done==1'b1) && (count5 == 5'b10100)) begin
        init_done_int <= 1'b1;
      //synthesis translate_off
        $display ("Calibration completed");
      //synthesis translate_on
      end else
        init_done_int <= init_done_int;
   end

   assign ctrl_init_done      = init_done_int;

   always @ (posedge clk_0)
     init_done <= init_done_int;

   assign burst_cnt           = (BURST_LENGTH_VALUE == 3'b010) ? 3'b010 :
          (BURST_LENGTH_VALUE == 3'b011) ? 3'b100 : 3'b001;

   assign ddr_address_BL      = `row_address'h0002;

   always @ (posedge clk_0) begin
      if ((rst_r)|| (init_state == INIT_DEEP_MEMORY_ST))
         init_count[3:0] <= 4'b0000;
      else if (init_memory ) begin
         if (init_state==INIT_LOAD_MODE_REG_ST || init_state==INIT_PRECHARGE
             || init_state==INIT_AUTO_REFRESH || init_state==INIT_DUMMY_READ_CYCLES
             || init_state==INIT_INITCOUNT_200 || init_state==INIT_DEEP_MEMORY_ST)
           init_count[3:0] <= init_count[3:0] + 1;
         else if(init_count == 4'hA )
           init_count[3:0] <= 4'h0;
         else
           init_count[3:0] <= init_count[3:0];
      end
   end // always @ (posedge clk_0)

   always @ (posedge clk_0) begin
      if ((rst_r)|| (init_state == INIT_DEEP_MEMORY_ST))
        init_count_cp[3:0] <= 4'b0000;
      else if (init_memory  ) begin
         if (init_state == INIT_LOAD_MODE_REG_ST || init_state == INIT_PRECHARGE
             || init_state==INIT_AUTO_REFRESH || init_state==INIT_DUMMY_READ_CYCLES
             || init_state==INIT_INITCOUNT_200 || init_state==INIT_DEEP_MEMORY_ST)
           init_count_cp[3:0] <= init_count_cp[3:0] + 1;
         else if(init_count_cp == 4'hA )
           init_count_cp[3:0] <= 4'h0;
         else
           init_count_cp[3:0] <= init_count_cp[3:0];
      end
   end // always @ (posedge clk_0)

   always @ (posedge clk_0 ) begin
      if (rst_r)
        chip_cnt <= 2'b00;
      else if ( init_state ==INIT_DEEP_MEMORY_ST)
        chip_cnt <= chip_cnt + 2'b01;
      else
        chip_cnt <= chip_cnt;
   end

   // write burst count
   always @ (posedge clk_0) begin
      if (rst_r)
        wrburst_cnt[2:0] <= 3'b000;
      else if (write_state || dummy_write_state)
        wrburst_cnt[2:0] <= burst_cnt[2:0];
      else if (wrburst_cnt[2:0] != 3'b000)
        wrburst_cnt[2:0] <= wrburst_cnt[2:0] - 1;
      else
        wrburst_cnt[2:0] <= 3'b000;
   end

   // read burst count for state machine
   always @ (posedge clk_0) begin
      if (rst_r)
        read_burst_cnt[2:0] <= 3'b000;
      else if (read_state)
        read_burst_cnt[2:0] <= burst_cnt[2:0];
      else if (read_burst_cnt[2:0] != 3'b000)
        read_burst_cnt[2:0] <= read_burst_cnt[2:0] - 1;
      else
        read_burst_cnt[2:0] <= 3'b000;
   end

   // count to generate write enable to the data path
   always @ (posedge clk_0) begin
      if (rst_r)
        ctrl_WrEn_cnt[2:0] <= 3'b000;
      else if (wdf_rden_r || dummy_write_state_r)
        ctrl_WrEn_cnt[2:0] <= burst_cnt[2:0];
      else if (ctrl_WrEn_cnt[2:0] != 3'b000)
        ctrl_WrEn_cnt[2:0] <= ctrl_WrEn_cnt[2:0] -1;
      else
        ctrl_WrEn_cnt[2:0] <= 3'b000;
   end

   //write enable to data path

   always @ (ctrl_WrEn_cnt) begin
      if (ctrl_WrEn_cnt[2:0] != 3'b000)
        ctrl_WrEn_r <= 1'b1;
      else
        ctrl_WrEn_r <= 1'b0;
   end

   always @ (posedge clk_0) begin
      if (rst_r)
        ctrl_WrEn_r1 <= 1'b0;
      else
        ctrl_WrEn_r1 <= ctrl_WrEn_r;
   end

   assign ctrl_WrEn = (registered_dimm) ? ctrl_WrEn_r1 : ctrl_WrEn_r;

   // DQS reset to data path
   always @ (posedge clk_0) begin
      if (rst_r)
        ctrl_Dqs_Rst_r <= 1'b0;
      else if ((first_write_state) || (dummy_write_state_1))
        ctrl_Dqs_Rst_r <= 1'b1;
      else
        ctrl_Dqs_Rst_r <= 1'b0;
   end

   always@(posedge clk_0) begin
      if(rst_r)
        ctrl_Dqs_Rst_r1 <= 1'b0;
      else
        ctrl_Dqs_Rst_r1 <= ctrl_Dqs_Rst_r;
   end

   assign ctrl_Dqs_Rst = (registered_dimm) ? ctrl_Dqs_Rst_r1 : ctrl_Dqs_Rst_r;


   // DQS enable to data path

   always @ (posedge clk_0) begin
      if (rst_r)
         ctrl_Dqs_En_r <= 1'b0;
      else if ((write_state) ||(wrburst_cnt != 3'b000) || (dummy_write_state))
         ctrl_Dqs_En_r <= 1'b1;
      else
        ctrl_Dqs_En_r <= 1'b0;
   end

   always @(posedge clk_0) begin
      if(rst_r)
        ctrl_Dqs_En_r1 <= 1'b0;
      else
        ctrl_Dqs_En_r1 <= ctrl_Dqs_En_r;
   end

   assign ctrl_Dqs_En = (registered_dimm) ? ctrl_Dqs_En_r1 : ctrl_Dqs_En_r;

   // cas count
   always @ (posedge clk_0) begin
      if (rst_r)
        cas_count[2:0] <= 3'b000;
      else if (init_state == INIT_DUMMY_FIRST_READ)
        cas_count[2:0] <= CAS_LATENCY_VALUE + `registered;
      else if (cas_count[2:0] != 3'b000)
        cas_count[2:0] <= cas_count[2:0] - 1;
      else
        cas_count[2:0] <= 3'b000;
   end

   //dummy_read enable
   always @ (posedge clk_0) begin
      if (rst_r)
        dummy_read_en <= 1'b0;
      else if (init_state == INIT_DUMMY_READ)
        dummy_read_en <= 1'b1;
      else if (phy_Dly_Slct_Done == 1'b1)
        dummy_read_en <= 1'b0;