mem_interface_top_rd_data_0.txt

利用fpga读写ddr的源代码 实测可以使用

  endcase
 end
end


always @(posedge CLK)
begin
 if(rst_r)
    rd_en_rise[4] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (rise_clk_count1)
    3'b011 :
        rd_en_rise[4] <= rd_en_r2[1];

    3'b100 :
        rd_en_rise[4] <= rd_en_r3[1];

    3'b101:
        rd_en_rise[4] <= rd_en_r4[1];

    3'b110:
        rd_en_rise[4] <= rd_en_r5[1];

    3'b111:
        rd_en_rise[4] <= rd_en_r6[1];

    default :
        rd_en_rise[4] <= 1'b0;
  endcase
 end
end

always @(posedge CLK)
begin
 if(rst_r)
    rd_en_fall[4] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (fall_clk_count1)
    3'b011 :
        rd_en_fall[4] <= rd_en_r2[1];

    3'b100 :
        rd_en_fall[4] <= rd_en_r3[1];

    3'b101:
        rd_en_fall[4] <= rd_en_r4[1];

    3'b110:
        rd_en_fall[4] <= rd_en_r5[1];

    3'b111:
        rd_en_fall[4] <= rd_en_r6[1];

    default :
        rd_en_fall[4] <= 1'b0;
  endcase
 end
end


always @(posedge CLK)
begin
 if(rst_r)
    rd_en_rise[5] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (rise_clk_count1)
    3'b011 :
        rd_en_rise[5] <= rd_en_r2[1];

    3'b100 :
        rd_en_rise[5] <= rd_en_r3[1];

    3'b101:
        rd_en_rise[5] <= rd_en_r4[1];

    3'b110:
        rd_en_rise[5] <= rd_en_r5[1];

    3'b111:
        rd_en_rise[5] <= rd_en_r6[1];

    default :
        rd_en_rise[5] <= 1'b0;
  endcase
 end
end

always @(posedge CLK)
begin
 if(rst_r)
    rd_en_fall[5] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (fall_clk_count1)
    3'b011 :
        rd_en_fall[5] <= rd_en_r2[1];

    3'b100 :
        rd_en_fall[5] <= rd_en_r3[1];

    3'b101:
        rd_en_fall[5] <= rd_en_r4[1];

    3'b110:
        rd_en_fall[5] <= rd_en_r5[1];

    3'b111:
        rd_en_fall[5] <= rd_en_r6[1];

    default :
        rd_en_fall[5] <= 1'b0;
  endcase
 end
end


always @(posedge CLK)
begin
 if(rst_r)
    rd_en_rise[6] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (rise_clk_count1)
    3'b011 :
        rd_en_rise[6] <= rd_en_r2[1];

    3'b100 :
        rd_en_rise[6] <= rd_en_r3[1];

    3'b101:
        rd_en_rise[6] <= rd_en_r4[1];

    3'b110:
        rd_en_rise[6] <= rd_en_r5[1];

    3'b111:
        rd_en_rise[6] <= rd_en_r6[1];

    default :
        rd_en_rise[6] <= 1'b0;
  endcase
 end
end

always @(posedge CLK)
begin
 if(rst_r)
    rd_en_fall[6] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (fall_clk_count1)
    3'b011 :
        rd_en_fall[6] <= rd_en_r2[1];

    3'b100 :
        rd_en_fall[6] <= rd_en_r3[1];

    3'b101:
        rd_en_fall[6] <= rd_en_r4[1];

    3'b110:
        rd_en_fall[6] <= rd_en_r5[1];

    3'b111:
        rd_en_fall[6] <= rd_en_r6[1];

    default :
        rd_en_fall[6] <= 1'b0;
  endcase
 end
end


always @(posedge CLK)
begin
 if(rst_r)
    rd_en_rise[7] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (rise_clk_count1)
    3'b011 :
        rd_en_rise[7] <= rd_en_r2[1];

    3'b100 :
        rd_en_rise[7] <= rd_en_r3[1];

    3'b101:
        rd_en_rise[7] <= rd_en_r4[1];

    3'b110:
        rd_en_rise[7] <= rd_en_r5[1];

    3'b111:
        rd_en_rise[7] <= rd_en_r6[1];

    default :
        rd_en_rise[7] <= 1'b0;
  endcase
 end
end

always @(posedge CLK)
begin
 if(rst_r)
    rd_en_fall[7] <= 1'b0;
 else if(comp_done_r2)
 begin
  case (fall_clk_count1)
    3'b011 :
        rd_en_fall[7] <= rd_en_r2[1];

    3'b100 :
        rd_en_fall[7] <= rd_en_r3[1];

    3'b101:
        rd_en_fall[7] <= rd_en_r4[1];

    3'b110:
        rd_en_fall[7] <= rd_en_r5[1];

    3'b111:
        rd_en_fall[7] <= rd_en_r6[1];

    default :
        rd_en_fall[7] <= 1'b0;
  endcase
 end
end


     always @(posedge CLK) begin
        if(rst_r)
          begin
             fifo_rd_enable1 <= 1'b0;
             fifo_rd_enable  <= 1'b0;
          end
        else
          begin
             fifo_rd_enable1 <= rd_en_rise[0];
             fifo_rd_enable  <= fifo_rd_enable1;
          end
     end

   
  mem_interface_top_rd_data_fifo_0 rd_data_fifo0
        (
                     .CLK                    (CLK),
                     .RESET                  (RESET),
                     .READ_EN_DELAYED_RISE   (rd_en_rise[0]),
                     .READ_EN_DELAYED_FALL   (rd_en_fall[0]),
                     .FIRST_RISING           (first_rising_rden[0]),
                     .READ_DATA_RISE         (READ_DATA_RISE[7:0]),
                     .READ_DATA_FALL         (READ_DATA_FALL[7:0]),
                     .fifo_rd_enable         (fifo_rd_enable),
                     .READ_DATA_FIFO_RISE    (READ_DATA_FIFO_RISE[7:0]),
                     .READ_DATA_FIFO_FALL    (READ_DATA_FIFO_FALL[7:0]),
                     .READ_DATA_VALID        (read_data_valid0)
                     );



  mem_interface_top_rd_data_fifo_0 rd_data_fifo1
        (
                     .CLK                    (CLK),
                     .RESET                  (RESET),
                     .READ_EN_DELAYED_RISE   (rd_en_rise[1]),
                     .READ_EN_DELAYED_FALL   (rd_en_fall[1]),
                     .FIRST_RISING           (first_rising_rden[0]),
                     .READ_DATA_RISE         (READ_DATA_RISE[15:8]),
                     .READ_DATA_FALL         (READ_DATA_FALL[15:8]),
                     .fifo_rd_enable         (fifo_rd_enable),
                     .READ_DATA_FIFO_RISE    (READ_DATA_FIFO_RISE[15:8]),
                     .READ_DATA_FIFO_FALL    (READ_DATA_FIFO_FALL[15:8]),
                     .READ_DATA_VALID        (read_data_valid1)
                     );



  mem_interface_top_rd_data_fifo_0 rd_data_fifo2
        (
                     .CLK                    (CLK),
                     .RESET                  (RESET),
                     .READ_EN_DELAYED_RISE   (rd_en_rise[2]),
                     .READ_EN_DELAYED_FALL   (rd_en_fall[2]),
                     .FIRST_RISING           (first_rising_rden[0]),
                     .READ_DATA_RISE         (READ_DATA_RISE[23:16]),
                     .READ_DATA_FALL         (READ_DATA_FALL[23:16]),
                     .fifo_rd_enable         (fifo_rd_enable),
                     .READ_DATA_FIFO_RISE    (READ_DATA_FIFO_RISE[23:16]),
                     .READ_DATA_FIFO_FALL    (READ_DATA_FIFO_FALL[23:16]),
                     .READ_DATA_VALID        (read_data_valid2)
                     );



  mem_interface_top_rd_data_fifo_0 rd_data_fifo3
        (
                     .CLK                    (CLK),
                     .RESET                  (RESET),
                     .READ_EN_DELAYED_RISE   (rd_en_rise[3]),
                     .READ_EN_DELAYED_FALL   (rd_en_fall[3]),
                     .FIRST_RISING           (first_rising_rden[0]),
                     .READ_DATA_RISE         (READ_DATA_RISE[31:24]),
                     .READ_DATA_FALL         (READ_DATA_FALL[31:24]),
                     .fifo_rd_enable         (fifo_rd_enable),
                     .READ_DATA_FIFO_RISE    (READ_DATA_FIFO_RISE[31:24]),
                     .READ_DATA_FIFO_FALL    (READ_DATA_FIFO_FALL[31:24]),
                     .READ_DATA_VALID        (read_data_valid3)
                     );



  mem_interface_top_rd_data_fifo_0 rd_data_fifo4
        (
                     .CLK                    (CLK),
                     .RESET                  (RESET),
                     .READ_EN_DELAYED_RISE   (rd_en_rise[4]),
                     .READ_EN_DELAYED_FALL   (rd_en_fall[4]),
                     .FIRST_RISING           (first_rising_rden[1]),
                     .READ_DATA_RISE         (READ_DATA_RISE[39:32]),
                     .READ_DATA_FALL         (READ_DATA_FALL[39:32]),
                     .fifo_rd_enable         (fifo_rd_enable),
                     .READ_DATA_FIFO_RISE    (READ_DATA_FIFO_RISE[39:32]),
                     .READ_DATA_FIFO_FALL    (READ_DATA_FIFO_FALL[39:32]),
                     .READ_DATA_VALID        (read_data_valid4)
                     );



  mem_interface_top_rd_data_fifo_0 rd_data_fifo5
        (
                     .CLK                    (CLK),
                     .RESET                  (RESET),
                     .READ_EN_DELAYED_RISE   (rd_en_rise[5]),
                     .READ_EN_DELAYED_FALL   (rd_en_fall[5]),
                     .FIRST_RISING           (first_rising_rden[1]),
                     .READ_DATA_RISE         (READ_DATA_RISE[47:40]),
                     .READ_DATA_FALL         (READ_DATA_FALL[47:40]),
                     .fifo_rd_enable         (fifo_rd_enable),
                     .READ_DATA_FIFO_RISE    (READ_DATA_FIFO_RISE[47:40]),
                     .READ_DATA_FIFO_FALL    (READ_DATA_FIFO_FALL[47:40]),
                     .READ_DATA_VALID        (read_data_valid5)
                     );



  mem_interface_top_rd_data_fifo_0 rd_data_fifo6
        (
                     .CLK                    (CLK),
                     .RESET                  (RESET),
                     .READ_EN_DELAYED_RISE   (rd_en_rise[6]),
                     .READ_EN_DELAYED_FALL   (rd_en_fall[6]),
                     .FIRST_RISING           (first_rising_rden[1]),
                     .READ_DATA_RISE         (READ_DATA_RISE[55:48]),
                     .READ_DATA_FALL         (READ_DATA_FALL[55:48]),
                     .fifo_rd_enable         (fifo_rd_enable),
                     .READ_DATA_FIFO_RISE    (READ_DATA_FIFO_RISE[55:48]),
                     .READ_DATA_FIFO_FALL    (READ_DATA_FIFO_FALL[55:48]),
                     .READ_DATA_VALID        (read_data_valid6)
                     );



  mem_interface_top_rd_data_fifo_0 rd_data_fifo7
        (
                     .CLK                    (CLK),
                     .RESET                  (RESET),
                     .READ_EN_DELAYED_RISE   (rd_en_rise[7]),
                     .READ_EN_DELAYED_FALL   (rd_en_fall[7]),
                     .FIRST_RISING           (first_rising_rden[1]),
                     .READ_DATA_RISE         (READ_DATA_RISE[63:56]),
                     .READ_DATA_FALL         (READ_DATA_FALL[63:56]),
                     .fifo_rd_enable         (fifo_rd_enable),
                     .READ_DATA_FIFO_RISE    (READ_DATA_FIFO_RISE[63:56]),
                     .READ_DATA_FIFO_FALL    (READ_DATA_FIFO_FALL[63:56]),
                     .READ_DATA_VALID        (read_data_valid7)
                     );




endmodule