📄 adder4.rpt
字号:
23: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\edasl\addr8\adder4.rpt
adder4
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
cin : INPUT;
-- Node name is 'led0'
-- Equation name is 'led0', type is output
led0 = _LC8_A14;
-- Node name is 'led1'
-- Equation name is 'led1', type is output
led1 = _LC2_A16;
-- Node name is 'led2'
-- Equation name is 'led2', type is output
led2 = _LC1_A19;
-- Node name is 'led3'
-- Equation name is 'led3', type is output
led3 = _LC7_A19;
-- Node name is 'led4'
-- Equation name is 'led4', type is output
led4 = _LC5_A19;
-- Node name is 'led5'
-- Equation name is 'led5', type is output
led5 = _LC3_A21;
-- Node name is 'led6'
-- Equation name is 'led6', type is output
led6 = GND;
-- Node name is 'led7'
-- Equation name is 'led7', type is output
led7 = GND;
-- Node name is '|adder:adderx|:11'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ001);
_EQ001 = a0 & !b0 & !cin
# !a0 & b0 & !cin
# a0 & b0 & cin
# !a0 & !b0 & cin;
-- Node name is '|adder:adderx|:13'
-- Equation name is '_LC3_A14', type is buried
_LC3_A14 = LCELL( _EQ002);
_EQ002 = a0 & cin
# b0 & cin
# a0 & b0;
-- Node name is '|adder:adderx~54|:11'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = LCELL( _EQ003);
_EQ003 = a1 & !b1 & !_LC3_A14
# !a1 & b1 & !_LC3_A14
# a1 & b1 & _LC3_A14
# !a1 & !b1 & _LC3_A14;
-- Node name is '|adder:adderx~54|:13'
-- Equation name is '_LC6_A21', type is buried
_LC6_A21 = LCELL( _EQ004);
_EQ004 = a1 & _LC3_A14
# b1 & _LC3_A14
# a1 & b1;
-- Node name is '|adder:adderx~85|:11'
-- Equation name is '_LC4_A21', type is buried
_LC4_A21 = LCELL( _EQ005);
_EQ005 = a2 & !b2 & !_LC6_A21
# !a2 & b2 & !_LC6_A21
# a2 & b2 & _LC6_A21
# !a2 & !b2 & _LC6_A21;
-- Node name is '|adder:adderx~85|:13'
-- Equation name is '_LC7_A21', type is buried
_LC7_A21 = LCELL( _EQ006);
_EQ006 = a2 & _LC6_A21
# b2 & _LC6_A21
# a2 & b2;
-- Node name is '|adder:adderx~108|:11'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = LCELL( _EQ007);
_EQ007 = a3 & b3 & _LC7_A21
# !a3 & !b3 & _LC7_A21
# a3 & !b3 & !_LC7_A21
# !a3 & b3 & !_LC7_A21;
-- Node name is '|adder:adderx~108|:13'
-- Equation name is '_LC5_A21', type is buried
_LC5_A21 = LCELL( _EQ008);
_EQ008 = a3 & _LC7_A21
# b3 & _LC7_A21
# a3 & b3;
-- Node name is ':957'
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = LCELL( _EQ009);
_EQ009 = _LC1_A21 & !_LC2_A21 & !_LC4_A21;
-- Node name is ':1010'
-- Equation name is '_LC3_A16', type is buried
_LC3_A16 = LCELL( _EQ010);
_EQ010 = _LC2_A21 & !_LC8_A13
# _LC3_A13 & !_LC8_A13;
-- Node name is ':1058'
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = LCELL( _EQ011);
_EQ011 = !_LC2_A21 & !_LC3_A13 & !_LC8_A13;
-- Node name is '~1070~1'
-- Equation name is '~1070~1', location is LC6_A16, type is buried.
-- synthesized logic cell
_LC6_A16 = LCELL( _EQ012);
_EQ012 = _LC2_A21
# !_LC4_A21
# _LC1_A21;
-- Node name is ':1071'
-- Equation name is '_LC7_A16', type is buried
_LC7_A16 = LCELL( _EQ013);
_EQ013 = _LC5_A16 & _LC6_A16
# !_LC2_A13 & _LC6_A16
# !_LC7_A13;
-- Node name is '~1433~1'
-- Equation name is '~1433~1', location is LC3_A13, type is buried.
-- synthesized logic cell
!_LC3_A13 = _LC3_A13~NOT;
_LC3_A13~NOT = LCELL( _EQ014);
_EQ014 = _LC1_A21 & _LC4_A21;
-- Node name is ':1766'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = LCELL( _EQ015);
_EQ015 = _LC4_A16 & _LC5_A16
# !_LC7_A13;
-- Node name is ':1796'
-- Equation name is '_LC8_A13', type is buried
!_LC8_A13 = _LC8_A13~NOT;
_LC8_A13~NOT = LCELL( _EQ016);
_EQ016 = _LC4_A21
# !_LC1_A21;
-- Node name is '~1819~1'
-- Equation name is '~1819~1', location is LC4_A16, type is buried.
-- synthesized logic cell
!_LC4_A16 = _LC4_A16~NOT;
_LC4_A16~NOT = LCELL( _EQ017);
_EQ017 = !_LC2_A13
# !_LC6_A16;
-- Node name is ':1819'
-- Equation name is '_LC2_A19', type is buried
_LC2_A19 = LCELL( _EQ018);
_EQ018 = _LC4_A16 & _LC7_A13 & _LC8_A13;
-- Node name is ':1849'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = LCELL( _EQ019);
_EQ019 = _LC1_A21 & _LC2_A21 & !_LC4_A21;
-- Node name is ':1867'
-- Equation name is '_LC8_A16', type is buried
_LC8_A16 = LCELL( _EQ020);
_EQ020 = !_LC2_A13 & _LC6_A16 & _LC7_A13
# _LC1_A13 & _LC6_A16 & _LC7_A13;
-- Node name is '~1950~1'
-- Equation name is '~1950~1', location is LC7_A13, type is buried.
-- synthesized logic cell
_LC7_A13 = LCELL( _EQ021);
_EQ021 = !_LC2_A21
# _LC4_A21
# _LC1_A21;
-- Node name is '~1950~2'
-- Equation name is '~1950~2', location is LC4_A13, type is buried.
-- synthesized logic cell
!_LC4_A13 = _LC4_A13~NOT;
_LC4_A13~NOT = LCELL( _EQ022);
_EQ022 = !_LC6_A13
# !_LC7_A13;
-- Node name is ':1950'
-- Equation name is '_LC3_A21', type is buried
_LC3_A21 = LCELL( _EQ023);
_EQ023 = a3 & _LC4_A13 & _LC7_A21
# b3 & _LC4_A13 & _LC7_A21
# a3 & b3 & _LC4_A13;
-- Node name is ':1954'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = LCELL( _EQ024);
_EQ024 = _LC8_A19
# _LC3_A19 & _LC4_A16 & !_LC5_A13;
-- Node name is '~1955~1'
-- Equation name is '~1955~1', location is LC2_A13, type is buried.
-- synthesized logic cell
!_LC2_A13 = _LC2_A13~NOT;
_LC2_A13~NOT = LCELL( _EQ025);
_EQ025 = !_LC1_A21 & _LC2_A21 & _LC4_A21;
-- Node name is '~1955~2'
-- Equation name is '~1955~2', location is LC3_A19, type is buried.
-- synthesized logic cell
_LC3_A19 = LCELL( _EQ026);
_EQ026 = !_LC5_A21 & _LC6_A13 & _LC7_A13;
-- Node name is ':1956'
-- Equation name is '_LC8_A19', type is buried
_LC8_A19 = LCELL( _EQ027);
_EQ027 = !_LC4_A13 & _LC5_A21
# _LC3_A16 & _LC4_A16 & _LC5_A21;
-- Node name is '~1960~1'
-- Equation name is '~1960~1', location is LC6_A13, type is buried.
-- synthesized logic cell
!_LC6_A13 = _LC6_A13~NOT;
_LC6_A13~NOT = LCELL( _EQ028);
_EQ028 = !_LC1_A21 & !_LC2_A21 & !_LC4_A21;
-- Node name is ':1960'
-- Equation name is '_LC7_A19', type is buried
_LC7_A19 = LCELL( _EQ029);
_EQ029 = _LC1_A16 & _LC5_A21 & _LC6_A13
# _LC6_A13 & _LC6_A19;
-- Node name is '~1961~1'
-- Equation name is '~1961~1', location is LC6_A19, type is buried.
-- synthesized logic cell
_LC6_A19 = LCELL( _EQ030);
_EQ030 = _LC4_A16 & _LC5_A13 & !_LC5_A21 & _LC7_A13;
-- Node name is ':1966'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = LCELL( _EQ031);
_EQ031 = _LC2_A19 & _LC5_A21
# _LC5_A21 & !_LC6_A13
# _LC4_A19;
-- Node name is ':1967'
-- Equation name is '_LC4_A19', type is buried
_LC4_A19 = LCELL( _EQ032);
_EQ032 = _LC3_A16 & _LC3_A19
# _LC3_A19 & !_LC4_A16;
-- Node name is ':1972'
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = LCELL( _EQ033);
_EQ033 = !_LC5_A21 & _LC6_A13 & _LC7_A16
# _LC5_A21 & !_LC6_A13
# _LC5_A21 & _LC8_A16;
-- Node name is ':1978'
-- Equation name is '_LC8_A14', type is buried
_LC8_A14 = LCELL( _LC1_A14);
Project Information f:\edasl\addr8\adder4.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,719K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -