📄 adder8s.rpt
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# !_LC2_C8 & !_LC5_C14 & _LC7_C14
# !_LC2_C8 & _LC5_C14 & !_LC7_C14;
-- Node name is '|adder8:u6|adder42:u1|adder:adderx~114|:13'
-- Equation name is '_LC4_C14', type is buried
_LC4_C14 = LCELL( _EQ008);
_EQ008 = _LC2_C8 & _LC7_C14
# _LC2_C8 & _LC5_C14
# _LC5_C14 & _LC7_C14;
-- Node name is '|adder8:u6|adder42:u2|adder:adderx|:11'
-- Equation name is '_LC2_C5', type is buried
_LC2_C5 = LCELL( _EQ009);
_EQ009 = _LC4_C14 & _LC6_C5 & _LC7_C5
# _LC4_C14 & !_LC6_C5 & !_LC7_C5
# !_LC4_C14 & !_LC6_C5 & _LC7_C5
# !_LC4_C14 & _LC6_C5 & !_LC7_C5;
-- Node name is '|adder8:u6|adder42:u2|adder:adderx|:13'
-- Equation name is '_LC1_C5', type is buried
_LC1_C5 = LCELL( _EQ010);
_EQ010 = _LC4_C14 & _LC7_C5
# _LC4_C14 & _LC6_C5
# _LC6_C5 & _LC7_C5;
-- Node name is '|adder8:u6|adder42:u2|adder:adderx~61|:11'
-- Equation name is '_LC6_C7', type is buried
_LC6_C7 = LCELL( _EQ011);
_EQ011 = _LC1_C5 & _LC7_C7 & _LC8_C7
# _LC1_C5 & !_LC7_C7 & !_LC8_C7
# !_LC1_C5 & !_LC7_C7 & _LC8_C7
# !_LC1_C5 & _LC7_C7 & !_LC8_C7;
-- Node name is '|adder8:u6|adder42:u2|adder:adderx~61|:13'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = LCELL( _EQ012);
_EQ012 = _LC1_C5 & _LC8_C7
# _LC1_C5 & _LC7_C7
# _LC7_C7 & _LC8_C7;
-- Node name is '|adder8:u6|adder42:u2|adder:adderx~91|:11'
-- Equation name is '_LC4_C8', type is buried
_LC4_C8 = LCELL( _EQ013);
_EQ013 = _LC1_C7 & _LC7_C8 & _LC8_C8
# _LC1_C7 & !_LC7_C8 & !_LC8_C8
# !_LC1_C7 & !_LC7_C8 & _LC8_C8
# !_LC1_C7 & _LC7_C8 & !_LC8_C8;
-- Node name is '|adder8:u6|adder42:u2|adder:adderx~91|:13'
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = LCELL( _EQ014);
_EQ014 = _LC1_C7 & _LC8_C8
# _LC1_C7 & _LC7_C8
# _LC7_C8 & _LC8_C8;
-- Node name is '|adder8:u6|adder42:u2|adder:adderx~114|:11'
-- Equation name is '_LC6_C14', type is buried
_LC6_C14 = LCELL( _EQ015);
_EQ015 = _LC1_C8 & _LC1_C14 & _LC2_C14
# _LC1_C8 & !_LC1_C14 & !_LC2_C14
# !_LC1_C8 & _LC1_C14 & !_LC2_C14
# !_LC1_C8 & !_LC1_C14 & _LC2_C14;
-- Node name is '|adder8:u6|adder42:u2|adder:adderx~114|:13'
-- Equation name is '_LC4_C10', type is buried
_LC4_C10 = LCELL( _EQ016);
_EQ016 = _LC1_C8 & _LC1_C14
# _LC1_C8 & _LC2_C14
# _LC1_C14 & _LC2_C14;
-- Node name is '|reg4:u2|:7'
-- Equation name is '_LC7_C14', type is buried
_LC7_C14 = DFFE( _EQ017, sc, VCC, VCC, VCC);
_EQ017 = _LC7_C14 & x2
# _LC7_C14 & x1
# l3 & !x1 & !x2;
-- Node name is '|reg4:u2|:9'
-- Equation name is '_LC6_C8', type is buried
_LC6_C8 = DFFE( _EQ018, sc, VCC, VCC, VCC);
_EQ018 = _LC6_C8 & x2
# _LC6_C8 & x1
# l2 & !x1 & !x2;
-- Node name is '|reg4:u2|:11'
-- Equation name is '_LC5_C7', type is buried
_LC5_C7 = DFFE( _EQ019, sc, VCC, VCC, VCC);
_EQ019 = _LC5_C7 & x2
# _LC5_C7 & x1
# l1 & !x1 & !x2;
-- Node name is '|reg4:u2|:13'
-- Equation name is '_LC5_C5', type is buried
_LC5_C5 = DFFE( _EQ020, sc, VCC, VCC, VCC);
_EQ020 = _LC5_C5 & x2
# _LC5_C5 & x1
# l0 & !x1 & !x2;
-- Node name is '|reg4:u3|:7'
-- Equation name is '_LC1_C14', type is buried
_LC1_C14 = DFFE( _EQ021, sc, VCC, VCC, VCC);
_EQ021 = _LC1_C14 & !x2
# _LC1_C14 & x1
# l3 & !x1 & x2;
-- Node name is '|reg4:u3|:9'
-- Equation name is '_LC8_C8', type is buried
_LC8_C8 = DFFE( _EQ022, sc, VCC, VCC, VCC);
_EQ022 = _LC8_C8 & !x2
# _LC8_C8 & x1
# l2 & !x1 & x2;
-- Node name is '|reg4:u3|:11'
-- Equation name is '_LC8_C7', type is buried
_LC8_C7 = DFFE( _EQ023, sc, VCC, VCC, VCC);
_EQ023 = _LC8_C7 & !x2
# _LC8_C7 & x1
# l1 & !x1 & x2;
-- Node name is '|reg4:u3|:13'
-- Equation name is '_LC7_C5', type is buried
_LC7_C5 = DFFE( _EQ024, sc, VCC, VCC, VCC);
_EQ024 = _LC7_C5 & !x2
# _LC7_C5 & x1
# l0 & !x1 & x2;
-- Node name is '|reg4:u4|:7'
-- Equation name is '_LC5_C14', type is buried
_LC5_C14 = DFFE( _EQ025, sc, VCC, VCC, VCC);
_EQ025 = _LC5_C14 & x2
# _LC5_C14 & !x1
# l3 & x1 & !x2;
-- Node name is '|reg4:u4|:9'
-- Equation name is '_LC3_C8', type is buried
_LC3_C8 = DFFE( _EQ026, sc, VCC, VCC, VCC);
_EQ026 = _LC3_C8 & x2
# _LC3_C8 & !x1
# l2 & x1 & !x2;
-- Node name is '|reg4:u4|:11'
-- Equation name is '_LC4_C7', type is buried
_LC4_C7 = DFFE( _EQ027, sc, VCC, VCC, VCC);
_EQ027 = _LC4_C7 & x2
# _LC4_C7 & !x1
# l1 & x1 & !x2;
-- Node name is '|reg4:u4|:13'
-- Equation name is '_LC4_C5', type is buried
_LC4_C5 = DFFE( _EQ028, sc, VCC, VCC, VCC);
_EQ028 = _LC4_C5 & x2
# _LC4_C5 & !x1
# l0 & x1 & !x2;
-- Node name is '|reg4:u5|:7'
-- Equation name is '_LC2_C14', type is buried
_LC2_C14 = DFFE( _EQ029, sc, VCC, VCC, VCC);
_EQ029 = _LC2_C14 & !x2
# _LC2_C14 & !x1
# l3 & x1 & x2;
-- Node name is '|reg4:u5|:9'
-- Equation name is '_LC7_C8', type is buried
_LC7_C8 = DFFE( _EQ030, sc, VCC, VCC, VCC);
_EQ030 = _LC7_C8 & !x2
# _LC7_C8 & !x1
# l2 & x1 & x2;
-- Node name is '|reg4:u5|:11'
-- Equation name is '_LC7_C7', type is buried
_LC7_C7 = DFFE( _EQ031, sc, VCC, VCC, VCC);
_EQ031 = _LC7_C7 & !x2
# _LC7_C7 & !x1
# l1 & x1 & x2;
-- Node name is '|reg4:u5|:13'
-- Equation name is '_LC6_C5', type is buried
_LC6_C5 = DFFE( _EQ032, sc, VCC, VCC, VCC);
_EQ032 = _LC6_C5 & !x2
# _LC6_C5 & !x1
# l0 & x1 & x2;
Project Information f:\edasl\addr8\adder8s.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 23,710K
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