📄 adder8s.rpt
字号:
41 - - - 31 INPUT ^ 0 0 0 4 l1
39 - - - 33 INPUT ^ 0 0 0 4 l2
38 - - - 34 INPUT ^ 0 0 0 4 l3
43 - - - 30 INPUT ^ 0 0 0 16 sc
44 - - - 29 INPUT ^ 0 0 0 16 x1
46 - - - 27 INPUT ^ 0 0 0 16 x2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\edasl\addr8\adder8s.rpt
adder8s
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
118 - - - 09 OUTPUT 0 1 0 0 co
114 - - - 06 OUTPUT 0 1 0 0 s0
117 - - - 08 OUTPUT 0 1 0 0 s1
116 - - - 07 OUTPUT 0 1 0 0 s2
119 - - - 13 OUTPUT 0 1 0 0 s3
12 - - C -- OUTPUT 0 1 0 0 s4
17 - - C -- OUTPUT 0 1 0 0 s5
14 - - C -- OUTPUT 0 1 0 0 s6
18 - - C -- OUTPUT 0 1 0 0 s7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\edasl\addr8\adder8s.rpt
adder8s
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - C 05 OR2 1 2 1 0 |adder8:u6|adder42:u1|adder:adderx|:11
- 8 - C 05 OR2 1 2 0 2 |adder8:u6|adder42:u1|adder:adderx|:13
- 3 - C 07 OR2 0 3 1 0 |adder8:u6|adder42:u1|adder:adderx~61|:11
- 2 - C 07 OR2 0 3 0 2 |adder8:u6|adder42:u1|adder:adderx~61|:13
- 5 - C 08 OR2 0 3 1 0 |adder8:u6|adder42:u1|adder:adderx~91|:11
- 2 - C 08 OR2 0 3 0 2 |adder8:u6|adder42:u1|adder:adderx~91|:13
- 3 - C 14 OR2 0 3 1 0 |adder8:u6|adder42:u1|adder:adderx~114|:11
- 4 - C 14 OR2 0 3 0 2 |adder8:u6|adder42:u1|adder:adderx~114|:13
- 2 - C 05 OR2 0 3 1 0 |adder8:u6|adder42:u2|adder:adderx|:11
- 1 - C 05 OR2 0 3 0 2 |adder8:u6|adder42:u2|adder:adderx|:13
- 6 - C 07 OR2 0 3 1 0 |adder8:u6|adder42:u2|adder:adderx~61|:11
- 1 - C 07 OR2 0 3 0 2 |adder8:u6|adder42:u2|adder:adderx~61|:13
- 4 - C 08 OR2 0 3 1 0 |adder8:u6|adder42:u2|adder:adderx~91|:11
- 1 - C 08 OR2 0 3 0 2 |adder8:u6|adder42:u2|adder:adderx~91|:13
- 6 - C 14 OR2 0 3 1 0 |adder8:u6|adder42:u2|adder:adderx~114|:11
- 4 - C 10 OR2 0 3 1 0 |adder8:u6|adder42:u2|adder:adderx~114|:13
- 7 - C 14 DFFE 4 0 0 2 |reg4:u2|:7
- 6 - C 08 DFFE 4 0 0 2 |reg4:u2|:9
- 5 - C 07 DFFE 4 0 0 2 |reg4:u2|:11
- 5 - C 05 DFFE 4 0 0 2 |reg4:u2|:13
- 1 - C 14 DFFE 4 0 0 2 |reg4:u3|:7
- 8 - C 08 DFFE 4 0 0 2 |reg4:u3|:9
- 8 - C 07 DFFE 4 0 0 2 |reg4:u3|:11
- 7 - C 05 DFFE 4 0 0 2 |reg4:u3|:13
- 5 - C 14 DFFE 4 0 0 2 |reg4:u4|:7
- 3 - C 08 DFFE 4 0 0 2 |reg4:u4|:9
- 4 - C 07 DFFE 4 0 0 2 |reg4:u4|:11
- 4 - C 05 DFFE 4 0 0 2 |reg4:u4|:13
- 2 - C 14 DFFE 4 0 0 2 |reg4:u5|:7
- 7 - C 08 DFFE 4 0 0 2 |reg4:u5|:9
- 7 - C 07 DFFE 4 0 0 2 |reg4:u5|:11
- 6 - C 05 DFFE 4 0 0 2 |reg4:u5|:13
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\edasl\addr8\adder8s.rpt
adder8s
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 13/144( 9%) 8/ 72( 11%) 0/ 72( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
29: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\edasl\addr8\adder8s.rpt
adder8s
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 sc
Device-Specific Information: f:\edasl\addr8\adder8s.rpt
adder8s
** EQUATIONS **
cin : INPUT;
l0 : INPUT;
l1 : INPUT;
l2 : INPUT;
l3 : INPUT;
sc : INPUT;
x1 : INPUT;
x2 : INPUT;
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC4_C10;
-- Node name is 's0'
-- Equation name is 's0', type is output
s0 = _LC3_C5;
-- Node name is 's1'
-- Equation name is 's1', type is output
s1 = _LC3_C7;
-- Node name is 's2'
-- Equation name is 's2', type is output
s2 = _LC5_C8;
-- Node name is 's3'
-- Equation name is 's3', type is output
s3 = _LC3_C14;
-- Node name is 's4'
-- Equation name is 's4', type is output
s4 = _LC2_C5;
-- Node name is 's5'
-- Equation name is 's5', type is output
s5 = _LC6_C7;
-- Node name is 's6'
-- Equation name is 's6', type is output
s6 = _LC4_C8;
-- Node name is 's7'
-- Equation name is 's7', type is output
s7 = _LC6_C14;
-- Node name is '|adder8:u6|adder42:u1|adder:adderx|:11'
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = LCELL( _EQ001);
_EQ001 = cin & _LC4_C5 & _LC5_C5
# cin & !_LC4_C5 & !_LC5_C5
# !cin & !_LC4_C5 & _LC5_C5
# !cin & _LC4_C5 & !_LC5_C5;
-- Node name is '|adder8:u6|adder42:u1|adder:adderx|:13'
-- Equation name is '_LC8_C5', type is buried
_LC8_C5 = LCELL( _EQ002);
_EQ002 = cin & _LC5_C5
# cin & _LC4_C5
# _LC4_C5 & _LC5_C5;
-- Node name is '|adder8:u6|adder42:u1|adder:adderx~61|:11'
-- Equation name is '_LC3_C7', type is buried
_LC3_C7 = LCELL( _EQ003);
_EQ003 = _LC4_C7 & _LC5_C7 & _LC8_C5
# !_LC4_C7 & !_LC5_C7 & _LC8_C5
# !_LC4_C7 & _LC5_C7 & !_LC8_C5
# _LC4_C7 & !_LC5_C7 & !_LC8_C5;
-- Node name is '|adder8:u6|adder42:u1|adder:adderx~61|:13'
-- Equation name is '_LC2_C7', type is buried
_LC2_C7 = LCELL( _EQ004);
_EQ004 = _LC5_C7 & _LC8_C5
# _LC4_C7 & _LC8_C5
# _LC4_C7 & _LC5_C7;
-- Node name is '|adder8:u6|adder42:u1|adder:adderx~91|:11'
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = LCELL( _EQ005);
_EQ005 = _LC2_C7 & _LC3_C8 & _LC6_C8
# _LC2_C7 & !_LC3_C8 & !_LC6_C8
# !_LC2_C7 & !_LC3_C8 & _LC6_C8
# !_LC2_C7 & _LC3_C8 & !_LC6_C8;
-- Node name is '|adder8:u6|adder42:u1|adder:adderx~91|:13'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = LCELL( _EQ006);
_EQ006 = _LC2_C7 & _LC6_C8
# _LC2_C7 & _LC3_C8
# _LC3_C8 & _LC6_C8;
-- Node name is '|adder8:u6|adder42:u1|adder:adderx~114|:11'
-- Equation name is '_LC3_C14', type is buried
_LC3_C14 = LCELL( _EQ007);
_EQ007 = _LC2_C8 & _LC5_C14 & _LC7_C14
# _LC2_C8 & !_LC5_C14 & !_LC7_C14
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