📄 adder42.rpt
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Device-Specific Information: f:\edasl\addr8\adder42.rpt
adder42
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 24 OR2 3 0 1 0 |adder:adderx|:11
- 3 - A 24 OR2 3 0 0 2 |adder:adderx|:13
- 6 - A 24 OR2 2 1 1 0 |adder:adderx~61|:11
- 4 - A 24 OR2 2 1 0 2 |adder:adderx~61|:13
- 5 - A 24 OR2 2 1 1 0 |adder:adderx~91|:11
- 8 - A 24 OR2 2 1 0 2 |adder:adderx~91|:13
- 7 - A 24 OR2 2 1 1 0 |adder:adderx~114|:11
- 2 - A 24 OR2 2 1 1 0 |adder:adderx~114|:13
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\edasl\addr8\adder42.rpt
adder42
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 4/ 48( 8%) 3/16( 18%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\edasl\addr8\adder42.rpt
adder42
** EQUATIONS **
a40 : INPUT;
a41 : INPUT;
a42 : INPUT;
a43 : INPUT;
b40 : INPUT;
b41 : INPUT;
b42 : INPUT;
b43 : INPUT;
c4 : INPUT;
-- Node name is 'co4'
-- Equation name is 'co4', type is output
co4 = _LC2_A24;
-- Node name is 's40'
-- Equation name is 's40', type is output
s40 = _LC1_A24;
-- Node name is 's41'
-- Equation name is 's41', type is output
s41 = _LC6_A24;
-- Node name is 's42'
-- Equation name is 's42', type is output
s42 = _LC5_A24;
-- Node name is 's43'
-- Equation name is 's43', type is output
s43 = _LC7_A24;
-- Node name is '|adder:adderx|:11'
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ001);
_EQ001 = a40 & b40 & c4
# !a40 & !b40 & c4
# a40 & !b40 & !c4
# !a40 & b40 & !c4;
-- Node name is '|adder:adderx|:13'
-- Equation name is '_LC3_A24', type is buried
_LC3_A24 = LCELL( _EQ002);
_EQ002 = a40 & c4
# b40 & c4
# a40 & b40;
-- Node name is '|adder:adderx~61|:11'
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = LCELL( _EQ003);
_EQ003 = a41 & b41 & _LC3_A24
# !a41 & !b41 & _LC3_A24
# a41 & !b41 & !_LC3_A24
# !a41 & b41 & !_LC3_A24;
-- Node name is '|adder:adderx~61|:13'
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = LCELL( _EQ004);
_EQ004 = a41 & _LC3_A24
# b41 & _LC3_A24
# a41 & b41;
-- Node name is '|adder:adderx~91|:11'
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = LCELL( _EQ005);
_EQ005 = a42 & b42 & _LC4_A24
# !a42 & !b42 & _LC4_A24
# a42 & !b42 & !_LC4_A24
# !a42 & b42 & !_LC4_A24;
-- Node name is '|adder:adderx~91|:13'
-- Equation name is '_LC8_A24', type is buried
_LC8_A24 = LCELL( _EQ006);
_EQ006 = a42 & _LC4_A24
# b42 & _LC4_A24
# a42 & b42;
-- Node name is '|adder:adderx~114|:11'
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = LCELL( _EQ007);
_EQ007 = a43 & b43 & _LC8_A24
# !a43 & !b43 & _LC8_A24
# a43 & !b43 & !_LC8_A24
# !a43 & b43 & !_LC8_A24;
-- Node name is '|adder:adderx~114|:13'
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = LCELL( _EQ008);
_EQ008 = a43 & _LC8_A24
# b43 & _LC8_A24
# a43 & b43;
Project Information f:\edasl\addr8\adder42.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,143K
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