📄 adder8.rpt
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p = Packed register
Device-Specific Information: f:\edasl\addr8\adder8.rpt
adder8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 0/ 48( 0%) 2/ 48( 4%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
B: 8/ 96( 8%) 6/ 48( 12%) 0/ 48( 0%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\edasl\addr8\adder8.rpt
adder8
** EQUATIONS **
a80 : INPUT;
a81 : INPUT;
a82 : INPUT;
a83 : INPUT;
a84 : INPUT;
a85 : INPUT;
a86 : INPUT;
a87 : INPUT;
b80 : INPUT;
b81 : INPUT;
b82 : INPUT;
b83 : INPUT;
b84 : INPUT;
b85 : INPUT;
b86 : INPUT;
b87 : INPUT;
c8 : INPUT;
-- Node name is 'co8'
-- Equation name is 'co8', type is output
co8 = _LC2_B11;
-- Node name is 's80'
-- Equation name is 's80', type is output
s80 = _LC5_A19;
-- Node name is 's81'
-- Equation name is 's81', type is output
s81 = _LC2_A19;
-- Node name is 's82'
-- Equation name is 's82', type is output
s82 = _LC7_A19;
-- Node name is 's83'
-- Equation name is 's83', type is output
s83 = _LC1_A19;
-- Node name is 's84'
-- Equation name is 's84', type is output
s84 = _LC8_B11;
-- Node name is 's85'
-- Equation name is 's85', type is output
s85 = _LC4_B11;
-- Node name is 's86'
-- Equation name is 's86', type is output
s86 = _LC6_B11;
-- Node name is 's87'
-- Equation name is 's87', type is output
s87 = _LC1_B11;
-- Node name is '|adder42:u1|adder:adderx|:11'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = LCELL( _EQ001);
_EQ001 = a80 & b80 & c8
# !a80 & !b80 & c8
# a80 & !b80 & !c8
# !a80 & b80 & !c8;
-- Node name is '|adder42:u1|adder:adderx|:13'
-- Equation name is '_LC4_A19', type is buried
_LC4_A19 = LCELL( _EQ002);
_EQ002 = a80 & c8
# b80 & c8
# a80 & b80;
-- Node name is '|adder42:u1|adder:adderx~61|:11'
-- Equation name is '_LC2_A19', type is buried
_LC2_A19 = LCELL( _EQ003);
_EQ003 = a81 & b81 & _LC4_A19
# !a81 & !b81 & _LC4_A19
# a81 & !b81 & !_LC4_A19
# !a81 & b81 & !_LC4_A19;
-- Node name is '|adder42:u1|adder:adderx~61|:13'
-- Equation name is '_LC6_A19', type is buried
_LC6_A19 = LCELL( _EQ004);
_EQ004 = a81 & _LC4_A19
# b81 & _LC4_A19
# a81 & b81;
-- Node name is '|adder42:u1|adder:adderx~91|:11'
-- Equation name is '_LC7_A19', type is buried
_LC7_A19 = LCELL( _EQ005);
_EQ005 = a82 & b82 & _LC6_A19
# !a82 & !b82 & _LC6_A19
# a82 & !b82 & !_LC6_A19
# !a82 & b82 & !_LC6_A19;
-- Node name is '|adder42:u1|adder:adderx~91|:13'
-- Equation name is '_LC8_A19', type is buried
_LC8_A19 = LCELL( _EQ006);
_EQ006 = a82 & _LC6_A19
# b82 & _LC6_A19
# a82 & b82;
-- Node name is '|adder42:u1|adder:adderx~114|:11'
-- Equation name is '_LC1_A19', type is buried
_LC1_A19 = LCELL( _EQ007);
_EQ007 = a83 & b83 & _LC8_A19
# !a83 & !b83 & _LC8_A19
# a83 & !b83 & !_LC8_A19
# !a83 & b83 & !_LC8_A19;
-- Node name is '|adder42:u1|adder:adderx~114|:13'
-- Equation name is '_LC3_A19', type is buried
_LC3_A19 = LCELL( _EQ008);
_EQ008 = a83 & _LC8_A19
# b83 & _LC8_A19
# a83 & b83;
-- Node name is '|adder42:u2|adder:adderx|:11'
-- Equation name is '_LC8_B11', type is buried
_LC8_B11 = LCELL( _EQ009);
_EQ009 = a84 & b84 & _LC3_A19
# !a84 & !b84 & _LC3_A19
# a84 & !b84 & !_LC3_A19
# !a84 & b84 & !_LC3_A19;
-- Node name is '|adder42:u2|adder:adderx|:13'
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ010);
_EQ010 = a84 & _LC3_A19
# b84 & _LC3_A19
# a84 & b84;
-- Node name is '|adder42:u2|adder:adderx~61|:11'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = LCELL( _EQ011);
_EQ011 = a85 & b85 & _LC3_B11
# !a85 & !b85 & _LC3_B11
# a85 & !b85 & !_LC3_B11
# !a85 & b85 & !_LC3_B11;
-- Node name is '|adder42:u2|adder:adderx~61|:13'
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = LCELL( _EQ012);
_EQ012 = a85 & _LC3_B11
# b85 & _LC3_B11
# a85 & b85;
-- Node name is '|adder42:u2|adder:adderx~91|:11'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = LCELL( _EQ013);
_EQ013 = a86 & b86 & _LC5_B11
# !a86 & !b86 & _LC5_B11
# a86 & !b86 & !_LC5_B11
# !a86 & b86 & !_LC5_B11;
-- Node name is '|adder42:u2|adder:adderx~91|:13'
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = LCELL( _EQ014);
_EQ014 = a86 & _LC5_B11
# b86 & _LC5_B11
# a86 & b86;
-- Node name is '|adder42:u2|adder:adderx~114|:11'
-- Equation name is '_LC1_B11', type is buried
_LC1_B11 = LCELL( _EQ015);
_EQ015 = a87 & b87 & _LC7_B11
# !a87 & !b87 & _LC7_B11
# a87 & !b87 & !_LC7_B11
# !a87 & b87 & !_LC7_B11;
-- Node name is '|adder42:u2|adder:adderx~114|:13'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ016);
_EQ016 = a87 & _LC7_B11
# b87 & _LC7_B11
# a87 & b87;
Project Information f:\edasl\addr8\adder8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,626K
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